What does this VHDL code do???

[thai.tony]

Hi all,

Sort of new to VHDL, and I am trying to understand some code so I can
translate it to Verilog.

LAST_BANKRW_PROCESS: process(Clk)
begin
....
last_row_lsb <= row_addr(12);
last_bank_lsb <= bank_addr(1);
...
end process LAST_BANKRW_PROCESS

same_row <= '1' when last_row_lsb = row_addr(12) else '0'
same_bank <= '1' when last_bank_lsb = row_bank(12) else '0'

-------------------------------------
// suppose to be a rising edge qualifier ???
XFERSIGS_RE_PROCESS: process(Clk)
begin
....
wr_req <= Bus_WrReq;
rd_req <= Bus_RdReq;
....
end process XFERSIGS_RE_PROCESS

wr_req_re <= Bus_WrReq and not(wr_req);
rd_req_re <= Bus_RdReq and not(rd_req);

**************************************************************************************

From my limited understanding, the LAST_BANKRW_PROCESS does nothing...

same_row and same_bank will alway be '1' because they will always equal
each other.

In XFERSIGS_RE_PROCESS, wr_req_re and rd_req_re will always be '0'
because it will be "0 and 1" or "1 and 0".

Is my understanding right? If not, please clearify. I am confused.

Thanks,
-Tony

 

[Brad Smallridge]

From my limited understanding, the LAST_BANKRW_PROCESS does nothing...

same_row and same_bank will alway be '1' because they will always equal
each other.

There is going to be a clock period when they are not the same.

In XFERSIGS_RE_PROCESS, wr_req_re and rd_req_re will always be '0'
because it will be "0 and 1" or "1 and 0".

Again, there will be a clock period when they will be 1 and 0 and this
corresponds
to a rising edge, and this code produces a oneshot output.

Brad Smallridge
Ai Vision

 

[Thomas Reinemann]

Hi all,

Sort of new to VHDL, and I am trying to understand some code so I can
translate it to Verilog.

LAST_BANKRW_PROCESS: process(Clk)
begin
....
last_row_lsb <= row_addr(12);
last_bank_lsb <= bank_addr(1);
...
end process LAST_BANKRW_PROCESS

same_row <= '1' when last_row_lsb = row_addr(12) else '0'
same_bank <= '1' when last_bank_lsb = row_bank(12) else '0'

The content of last_row_lsb is the value of row_addr(12) delayed by one
clock. Therefore same_row will be '0' on *each* edge of row_addr(12).

By Tom

 

[thai.tony]

Thanks. You guys are bith right. I see it now. Thank you for the help.

-Tony