What graphical entry/documentation tools?

Discussion in 'VHDL' started by jamesp, Dec 8, 2005.

  1. jamesp

    jamesp Guest

    Hi,

    I am a mature student will be doing some complex VHDL and Verilog design
    work for my course. As well as having to create and test the
    functionality of the design (in both languages) I want to document how
    the design is put together and it's complex hierarchy.

    Is there anything out there that will allow me to represent my design in
    some sort of hierarchical functional blocks to use as a documentation
    tool? As I want to use both languages for the design something that
    ideally can accommodate VHDL and Verilog.

    I am happy using my normal editing system for the code design so I don't
    want a 'block-to-code' type of system.

    Thanks for your help.

    James.
     
    jamesp, Dec 8, 2005
    #1
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  2. jamesp wrote:

    > I am a mature student will be doing some complex VHDL and Verilog design
    > work for my course. As well as having to create and test the
    > functionality of the design (in both languages) I want to document how
    > the design is put together and it's complex hierarchy.


    If you have an audience for such artwork,
    it is much easier to obtain when the design
    is complete. Synthesis programs have an
    rtl viewer that will do the work for you.
    I sketch diagrams in my notebook to get
    started. Things usually change significantly
    before I am done.

    -- Mike Treseler
     
    Mike Treseler, Dec 8, 2005
    #2
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  3. jamesp

    Brian Guest

    jamesp wrote:
    > Hi,
    >
    > I am a mature student will be doing some complex VHDL and Verilog design
    > work for my course. As well as having to create and test the
    > functionality of the design (in both languages) I want to document how
    > the design is put together and it's complex hierarchy.
    >
    > Is there anything out there that will allow me to represent my design in
    > some sort of hierarchical functional blocks to use as a documentation
    > tool? As I want to use both languages for the design something that
    > ideally can accommodate VHDL and Verilog.
    >
    > I am happy using my normal editing system for the code design so I don't
    > want a 'block-to-code' type of system.
    >
    > Thanks for your help.
    >
    > James.


    Hi James,

    We have a tool which we believe will address your questions. There is a
    15 day fully functional evaluation download available on the web site so
    please feel free to try it out.

    www.expressivesystems.com

    --

    Cheers
    Brian
    ___________________________________
    Expressive Systems.
    www.expressivesystems.com
     
    Brian, Dec 9, 2005
    #3
  4. jamesp

    Guest

  5. jamesp

    Hans Guest

    Hi James,

    Have a look at Mentor's HDL Designer. It has a lot of graphical design entry
    methods like block diagrams, graphical FSM (+ animation during simulation if
    you have Modelsim), flow charts, IBD (spreadsheet like entry method) etc It
    now also includes a design checker (ex Design Analyst). It supports OLE so
    you can drag and drop diagrams into Office products (not the open flavour
    :). It also supports export to HTML including all your side data (scripts,
    pdf documents etc).

    You might also want to look at tools similar to Java-Doc to automatically
    create documentation,

    Hans
    www.ht-lab.com



    "jamesp" <> wrote in message
    news:dn90qh$8m3$...
    > Hi,
    >
    > I am a mature student will be doing some complex VHDL and Verilog design
    > work for my course. As well as having to create and test the functionality
    > of the design (in both languages) I want to document how the design is put
    > together and it's complex hierarchy.
    >
    > Is there anything out there that will allow me to represent my design in
    > some sort of hierarchical functional blocks to use as a documentation
    > tool? As I want to use both languages for the design something that
    > ideally can accommodate VHDL and Verilog.
    >
    > I am happy using my normal editing system for the code design so I don't
    > want a 'block-to-code' type of system.
    >
    > Thanks for your help.
    >
    > James.
     
    Hans, Dec 9, 2005
    #5
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