what happens if sensitivity of a combinatorial process is incomplete?

Discussion in 'VHDL' started by xohaibhassan, Feb 6, 2011.

  1. xohaibhassan

    xohaibhassan

    Joined:
    Feb 6, 2011
    Messages:
    1
    Hi ,

    I am just going through the lecture slides of my course "Digital design with FPGA" , i am a bit confused and i have some questions , i will appreciate if somebody helps me in understanding the concepts .

    My questions are
    1)
    what happens if an input signal is missing in the sensitivity list of a combinatorial process? My teacher told me to include all the input signals in the sensitivity list ,but why ,it just came to my mind .

    process(a,b,c)
    begin
    y=a or b or c;
    end process;

    what basically happens if one of the inputs is skipped?

    2) what is the difference between a vhdl signal and variable? what must be the criteria to select between both?

    3) why latches are a always discouraged for fpgaz ?
    xohaibhassan, Feb 6, 2011
    #1
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  2. xohaibhassan

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    1) while simulating, only updates to signals in the sensitivity list trigger the process code to be executed. When you miss a signal in the list, updates to
    that signal won't have any affect (the process code is not executed) unless another signal gets an update as well.

    2) a variable gives you software-like behavior inside a process/function/procedure.
    In a process, you need signals to communicate inputs/results with the rest of the architecture body.

    The update semantics of signals vs variables are different. Updating a signal value will only have affect after a "delta" time. That means, reading the signal inside the process will always give the original value:
    Code:
    signal x, y, z : std_logic;
    
    process(a) is
    begin
      x <= a and y;
      z <= x;
    end process
    
    After execution of this process, z will have the previous value of x and x will hold the calculated value.

    In contrast:
    Code:
    signal x, y, z : std_logic;
    
    process(a) is
      variable vx, vz : std_logic;
    begin
      vx := a and y;
      vz := vx;
      x <= vx;
      z <= vz;
    end process
    
    Variables are updated immediately and can be used as intermediate values.
    x and z will both hold the calculated value.

    3) Latches are generally to be avoided because their use can cause unwanted behavior.

    After a clock level change, new values are calculated throughout the system.
    Depending on timings, a component might read old values from one component and new values from another and reevaluate, generating nonsensical output. With flipflops this is avoided as, between the clock edges, no component can (incorrectly) act on inputs again
    (Hoping that is a correct explanation!)
    joris, Feb 8, 2011
    #2
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