What is a signal?

Discussion in 'VHDL' started by valtih1978, Jan 26, 2013.

  1. valtih1978

    valtih1978 Guest

    Does

    signal A: bit_vector(1 to 5);

    define 1 signal, A or 5 elementary signals or 6 signals, one for A and 5
    elements?

    Is A(3 to 5) also a signal? If so, then, does the declaration define
    2^32 signals, for every aggregate we can combine?

    What is the target signal in 'A(1) <= value'? Is it an element,
    composite or both?
    valtih1978, Jan 26, 2013
    #1
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  2. valtih1978

    rickman Guest

    On 1/26/2013 6:41 PM, Alan Fitch wrote:
    > On 26/01/13 16:18, valtih1978 wrote:
    >> Does
    >>
    >> signal A: bit_vector(1 to 5);
    >>
    >> define 1 signal, A or 5 elementary signals or 6 signals, one for A and 5
    >> elements?
    >>
    >> Is A(3 to 5) also a signal? If so, then, does the declaration define
    >> 2^32 signals, for every aggregate we can combine?
    >>
    >> What is the target signal in 'A(1)<= value'? Is it an element,
    >> composite or both?
    >>

    >
    > See section 4.3 of the 2002 LRM
    >
    > "There are four classes of objects: constants, signals, variables, and
    > files. The variable class of objects also has an additional subclass:
    > shared variables. The class of an explicitly declared object is
    > specified by the reserved word that must or may appear at the beginning
    > of the declaration of that object.
    >
    > For a given object of a composite type, each subelement of that object
    > is itself an object of the same class and subclass, if any, as the given
    > object. The value of a composite object is the aggregation of the values
    > of its subelements."
    >
    > So an element of signal A in your example is also a signal.


    He also asked about A(3 to 5) ect, but I don't think that makes 2^32
    signals. I think this makes 2^5 - 1 = 31. The null set of coefficients
    shouldn't be a signal... A() I mean.

    Rick
    rickman, Jan 28, 2013
    #2
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