Hi,
I want to know what is called carry chain structure in FPGA is called
in IC?
Thank you.
Weng
Weng, the objective of the carry chain is easily defined: It
facilitates binary addition and subtraction, where any bit position
can affect the next higher bit position with a binary carry or borrow
signal.
The physical implementation can vary a lot, using different
compromises between speed and complexity (and perhaps power
consumption). There is ripple carry, carry look-ahead, carry
anticipate, and even more exotic methods. The FPGAs I am familiar with
use carry-look-ahead over 2 or 4 bits, which is just one step ahead of
the simplest ripple-carry. But since the FPGA carry structure is hard-
wired, it usually is faster than any more exotic scheme, if ithat were
implemented in an FPGA. At least in the usual range below 32 bits...
ASIC trade-offs are different.
Peter Alfke