what is difference between generate and for loop in vhdl

Discussion in 'VHDL' started by pravin.vhdl, Aug 14, 2009.

  1. pravin.vhdl

    pravin.vhdl

    Joined:
    Jun 18, 2009
    Messages:
    11
    hello frnds can anybody help me reg:what is the diffrence between generate nd for loop..please give your valuable reply.........my advanced thanks to all.
    regards
    praveen
     
    pravin.vhdl, Aug 14, 2009
    #1
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