What is the meaning of a signal in VHDL

[parag_paul]

Hi All,
Is a signal in VHDL supposed to mean that we have a source in the
entity somewhere. Can there be any Verilog analogy to the signal in
VHDL
-Parag

 

[Frank Buss]

Is a signal in VHDL supposed to mean that we have a source in the
entity somewhere. Can there be any Verilog analogy to the signal in
VHDL

yes, it's called "wire" in Verilog.

 

[parag_paul]

As far as I believe, there is no concept of a single physical wire in
VHDL ,
what signals could have possibly meant and what I feel after reading
about it is that,it is a source in an entity. ( if we are to extentd
the concept of source to sink in VHDL )

 

[Pinhas]

(e-mail address removed) :

As far as I believe, there is no concept of a single physical wire in
VHDL ,
what signals could have possibly meant and what I feel after reading
about it is that,it is a source in an entity. ( if we are to extentd
the concept of source to sink in VHDL )

It Can be either a wire or reg, if I use verilog analogy. It depends
on the usage.
Pinhas
http://bknpk.no-ip.biz
http://bknpk.no-ip.biz/usb_1.html

 

[Frank Buss]

As far as I believe, there is no concept of a single physical wire in
VHDL ,

In VHDL you can define input and output signals in the "port" section. If
you use "signal" inside a "architecture" section in VHDL, it is really the
same like Verilog, because "wire" is not a physical wire in verilog, too
and doesn't need to be a single wire, e.g. you can write "wire [7:0]
my_bus;", which is the same like "signal my_bus : std_logic_vector(7 downto
0);" in VHDL. And in VHDL you can define single bit signals, too, like int
"signal my_bit : std_logic;".

what signals could have possibly meant and what I feel after reading
about it is that,it is a source in an entity. ( if we are to extentd
the concept of source to sink in VHDL )

No, it is more like a variable in computer programs. E.g. you can define a
state type like this:

type STATE_TYPE IS (IDLE, FOO, BAR);

Then you can use this type for a signal:

signal state : STATE_TYPE;

and in a process you can assign values to it and read from it:

process(reset, clk)
begin
if reset='1' then
state <= IDLE;
elsif rising_edge(clk) then
case state is
when IDLE =>
if something_interesting then
state <= FOO;
end if;
when FOO =>
if something_more_intersting then
state <= BAR;
end if;
when BAR =>
if unintersting then
state <= IDLE;
end if;
end case;
end if;
end process;

I think this is the same with "wire" in Verilog.

 

[parag_paul]

Actually in Verilog
you can never write on a wire

like

wire a;

initial
begin
a = 1;
#12
a<=1;
end


Does not work. it will not allow you to do so.
rather, you can have

reg b;
assign a= b;
where a is an wire.
Now when you do

initial
begin
b=1;
#1
=0;
end

THis will be a signal source for the wire a. So I am back to confusion

 

[Mike Treseler]

THis will be a signal source for the wire a. So I am back to confusion

One source of this confusion is that vhdl signals
(or verilog wires) are only strictly needed to wire up
entity/module instances in a structural design.

Signals/Wires are always required in a testbench
to hook up the UUT instance.

Here is a verilog synthesis module using no wires.

http://home.comcast.net/~mike_treseler/div10.v

Here are a few vhdl synthesis designs using no signals.

http://home.comcast.net/~mike_treseler/

-- Mike Treseler

 

[Frank Buss]

Actually in Verilog
you can never write on a wire

I don't know much about Verilog, but looks like you are right and the
semantic is a bit different. E.g. in this example:

http://www.asic-world.com/tidbits/verilog_fsm.html

there is a function, which calculates the value of a wire. The result is
the same, if you use signals in VHDL with the syntax I've shown in my
previous posting, in Verilog it is just a bit more cumbersome to write,
because you can assign a value only once to a wire. Maybe Mike is right and
using registers in Verilog and variables in VHDL is better, because it
leads to smaller and better to maintain programs.

 

[parag_paul]

Dues UUT mean unit under test ( the same thing we call DUT , design
under test
-Parag

 

[parag_paul]

So the needs only comes in the Test bench scenario. What Mike meant
( if I read between the lines )

An UUT does not require any signals or wires ? Is it?
What about Verilog signals at the top level. Do they give you any
requirement for wire at all ( obviously the top level more often then
not is a test bench)
is the top level module synthesizable
-Parag

 

[Frank Buss]

What about Verilog signals at the top level. Do they give you any
requirement for wire at all ( obviously the top level more often then
not is a test bench)

I don't know about Verilog, but in VHDL, you need signals at the top level
entity to interconnect the entities below it. E.g. assume you have an I2C
slave entity, which filters the device address. At the top level entity you
connect this to a signal and dispatch the data_out signal to different sub
entities, according to the I2C device address. For the rest of the internal
logic of an entity you don't need signals, but many designs uses it, maybe
because it is closer to the hardware and often VHDL designers are hardware
designers, not software programmers.

is the top level module synthesizable

Yes, if it is not a test bench with wait statements.

 

[Jonathan Bromley]

Is a signal in VHDL supposed to mean that we have a source in the
entity somewhere. Can there be any Verilog analogy to the signal in
VHDL

I fear the discussion has become a little confused
and bogged-down in details of style.

Verilog and VHDL, as simulation languages, have very
different notions of "signal" and "driver".

There is NO obvious analogy between VHDL and Verilog
simulation semantics, although you can (with care) get
both languages to do the same things for you.

However, whe writing RTL (synthesisable) code, you can
easily achieve equivalence between Verilog and VHDL.
Within a VHDL process you can make assignments to
two different kinds of thing: signals and variables.
Signals can be seen by other processes, but variables
are local to the process and cannot be seen outside
the process. Signals have delayed update, variables
update immediately. So here's how you mimic exactly
that in Verilog, WHEN YOU ARE CODING SYNTHESISABLE LOGIC:

VHDL signal:
~~~~~~~~~~~~
Use a Verilog variable that's declared at the top level
of a module. In an "always" block, make assignments
to that variable using nonblocking <= assignment.

VHDL variable:
~~~~~~~~~~~~~~
Use a Verilog variable that's declared locally within
a named begin...end block in an always block. Assign
to that variable using blocking = assignment.


Now, let's tell the story from a simulation point of view.

In VHDL, there are two different kinds of data object: signals
and variables. Variables work exactly like variables in software,
and are used to store values used in the computation performed
by a process. Variables are local to a process, and invisible
outside that process. Signals, on the other hand, carry values
from one process to another, and process execution can be
triggered by the change in value of a signal.
Every process that drives a given signal represents
a static, structural driver on that signal. The value driven
by the process's driver is determined by what the process
chooses to write to the signal. The updating of the value
on signals is performed at a time when no processes are
executing.

In Verilog, there are two different kinds of data object:
nets and variables. The most common form of net is 'wire'
and the most common form of variable is 'reg'.

Nets get their values from structural drivers, which
can be created in various ways:
- If you connect a net to the output of a module or primitive
instance, that output represents a structural driver
- A continuous assign statement to a net represents a
driver on that net
- Inside a module, an input port of the module represents
a structural driver on the corresponding internal net
and a few other, more exotic cases.

Variables, by contrast, get their values by procedural
assignment from code in an "initial" or "always" block.
Process execution can be triggered by value changes on
either nets or variables. To make this process triggering
less prone to race conditions, it's possible to update
variables using "nonblocking assignment" (<=) which,
a little like VHDL signal assignment, postpones updating
of the variable until *all* procedural code has reached
a delay statement or a sensitivity list.

Hope this helps point you in the right direction as you
search for a fuller understanding of the two languages.
--
Jonathan Bromley, Consultant

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[parag_paul]

Thanks a lot Jonathan
That helps

 

[Mike Treseler]

Maybe Mike is right and
using registers in Verilog and variables in VHDL is better, because it
leads to smaller and better to maintain programs.

That point has been subject to much debate,
but I will make the additional claim that
a signal-free vhdl design entity is much easier
to translate into a verilog module than any other style.

-- Mike Treseler