What is the purpose of an Architecture Identifier?

[Grant Robertson]

I am a student in a 100 level course on digital logic design using VHDL.
I do not expect to do much VHDL programming after this course. But there
is one thing I can't figure out and it is driving me nuts. I have Googled
till I am blue in the face. There are lots of references to "Architecture
Identifier" but I can't find anything that actually says what the
identifier of an Architecture block is for and how I should use it.

Why does an Architecture declaration have an identifier at all? You
already list the Entity Name in the same line. Why do you need yet
another name for the same thing? Where else is this identifier used? For
simple projects does it matter at all?

I have learned that a single Entity may have more than one Architecture
declared for it. Is this identifier just to differentiate between all of
the different Architectures that may have been declared for a particular
Entity? If so, do the Architecture identifiers need to be unique for the
entire project or just for each Entity? In other words, could I have an
entity named "ANDgate" with an Architecture named "behav" and an entity
named "ORgate" with an Architecture named "behav" and still have things
work fine? Or would I need to name the Architectures "ANDbehave" and
"ORbehave" respectively?

Thanks for any help.

 

[Andy Ray]

entire project or just for each Entity? In other words, could I have an
entity named "ANDgate" with an Architecture named "behav" and an entity
named "ORgate" with an Architecture named "behav" and still have things
work fine?

Yes.

The point is you can have multiple architectures, lets say "behav",
"rtl" and "structural", per entity. Have a look at configuration
statements to see how you can select which specific architecture you
want to use.

Cheers,

Andy

 

[David R Brooks]

Yes.

The point is you can have multiple architectures, lets say "behav",
"rtl" and "structural", per entity. Have a look at configuration
statements to see how you can select which specific architecture you
want to use.

The point of this being, that I could write a "behav" architecture,
without regard to it being synthesisable, & satisfy myself (& possibly
my customer) that it meets the requirements. Then I write a "rtl"
version, and test the two against each other. The rtl needs to be
synthesisable.
The synthesiser, in turn, outputs a "structural" version, which can be
tested against the others.

 

[Brian Drummond]

Yes.

The point is you can have multiple architectures, lets say "behav",
"rtl" and "structural", per entity. Have a look at configuration
statements to see how you can select which specific architecture you
want to use.

One use for this is to speed simulation of a component in a system - you
can use the "behav" architectures of the other components for faster
simulation, but the "rtl" or "structural" architectures of the devuce
under test.

Another is to use vendor-specific components in a portable design - if
you have architectures "xilinx", "altera" and "generic" for e.g. a
multiplier, you can take advantage of architecture specific features
without (too badly) compromising portability.

- Brian

 

[TigerJade]

I guess you still need to simulate the "slow" ones, otherwise you
cannot verify if the "slow" ones are functionally correct.