What to do when post-synthesis simulation do not pass

Discussion in 'VHDL' started by jasonL, Jun 3, 2007.

  1. jasonL

    jasonL

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    Mar 16, 2007
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    I write a module, behavior simulation is fine. Then, I synthesize it. It has no error. However, wen I run the post-synthesis simulation, the post-synthesis model do not function as behavior model.

    I guess I should rewrite the code in different style or using other synthesis tools. But before that, What should I do to findout what cause the mis-match in design?
     
    jasonL, Jun 3, 2007
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  2. jasonL

    quantum_dot

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    Nov 21, 2006
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    Generally when the post synthesis simulation is not giving correct results, you should look out for timing requirements. Please have a look on your timing closure result and you will definetly find the source of the problem. Have you already defined the required timing ocnstraints in your ucf file ?
     
    quantum_dot, Jun 4, 2007
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  3. jasonL

    jasonL

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    Thank you, quantum_dot

    The problem is that I have not defined the timing ocnstraints yet. It seems like sythesis problem.
     
    jasonL, Jun 4, 2007
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