what wrong with my code? Traffice light controller State Machine

[snjsteve]

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
use ieee.NUMERIC_STD.all;


ENTITY TRAFFIC_CONTROLLER IS


port(
CLOCK,RESET,CW_EW,CW_NS,EV: in std_logic;
RNS,REW,GNS,GEW,YNS,YEW: out std_logic;
NAS_COUNTER,EAW_COUNTER: out std_logic_vector(2 downto 0));

END TRAFFIC_CONTROLLER ;


ARCHITECTURE ASMArch OF TRAFFIC_CONTROLLER IS
TYPE ASMstateType IS (NorthandSouth,EastandWest,EMERGENCY,NAS_YELLOW,EAW_YELLOW,RED_STATE) ;
SIGNAL state,nextstate : ASMstateType ;
SIGNAL NS_COUNT,EW_COUNT: std_logic_vector(2 downto 0):="000";
SIGNAL YNS_COUNT,YEW_COUNT: std_logic_vector(1 downto 0):="00";
SIGNAL Where: std_logic:='0';
BEGIN

PROCESS ( Reset, Clock ) -- State transitions
BEGIN
IF Reset = '1' THEN -- reset is active low
state <= NorthandSouth;
ELSIF (Clock 'EVENT AND Clock = '1') THEN
State <= nextState;
END IF;
END PROCESS ;

PROCESS (state,EV,NS_COUNT,CW_EW,YNS_COUNT,CW_NS,EW_COUNT,YEW_COUNT,WHERE)

BEGIN

CASE state IS
WHEN NorthandSouth => ---NORTHANDSOUTH
REW <= '1';
where<='0';
IF EV = '1' THEN
STATE <= EMERGENCY;
ELSIF NS_COUNT < "101" THEN
NS_COUNT <= STD_LOGIC_VECTOR(UNSIGNED(NS_COUNT)+1);
nextState <= NorthandSouth;
ELSIF (CW_EW ='1' and NS_COUNT ="101") THEN
nextState <= NAS_YELLOW ;
NS_COUNT <= "001";
ELSIF CW_EW ='0' THEN
NS_COUNT<= STD_LOGIC_VECTOR(UNSIGNED(NS_COUNT)+1);
END IF;

WHEN NAS_YELLOW => ---NAS_YELLOW
YNS <= '1';
REW <= '1';
IF YNS_COUNT <= "10" then
YNS_COUNT <= "00";
nextState <= RED_STATE;
else
YNS_COUNT <= STD_LOGIC_VECTOR(UNSIGNED(YNS_COUNT)+1);
nextState <= NAS_YELLOW;
end IF;

WHEN EastandWest => ---EASTANDWEST
RNS <= '1';
where <='1';
IF EV = '1' THEN
STATE <= EMERGENCY;
ELSIF EW_COUNT < "101" THEN
EW_COUNT <= STD_LOGIC_VECTOR(UNSIGNED(EW_COUNT)+1);
nextState <= EASTANDWEST;
ELSIF (CW_NS ='1' and EW_COUNT ="101") THEN
nextState <= EAW_YELLOW ;
EW_COUNT <= "001";
ELSIF CW_EW ='0' THEN
EW_COUNT<= STD_LOGIC_VECTOR(UNSIGNED(EW_COUNT)+1);
END IF;

WHEN EAW_YELLOW => ---EAW_YELLOW
YEW <= '1';
RNS <= '1';
IF YEW_COUNT <= "10" then
YEW_COUNT <= "00";
nextState <= RED_STATE;
else
YEW_COUNT <= STD_LOGIC_VECTOR(UNSIGNED(YEW_COUNT)+1);
nextState <= EAW_YELLOW;
end IF;

WHEN RED_STATE => ---RED_STATE
REW <= '1';
RNS <= '1';
IF where='0' then
NEXTSTATE <= EASTANDWEST;
ELSIF where='1' THEN
NEXTSTATE <= NorthandSouth;
end IF;

WHEN EMERGENCY => ---EMERGENCY
IF where='0' then
YNS <= '1';
NEXTSTATE <= NAS_YELLOW;
ELSIF where='1' THEN
YEW <= '1';
NEXTSTATE <= EAW_YELLOW;
end IF;

WHEN OTHERS =>
nextState <= NorthandSouth;

END CASE ;
NAS_COUNTER <=NS_COUNT;
EAW_COUNTER <=EW_COUNT;
END PROCESS ;
END ASMArch ;


i keep getting
Error (10028): Can't resolve multiple constant drivers for net "state.NorthandSouth" at TrafficController.vhd(34)
Error (10029): Constant driver at TrafficController.vhd(25)
Error (10028): Can't resolve multiple constant drivers for net "state.EastandWest" at TrafficController.vhd(34)
Error (10028): Can't resolve multiple constant drivers for net "state.EMERGENCY" at TrafficController.vhd(34)
Error (10028): Can't resolve multiple constant drivers for net "state.NAS_YELLOW" at TrafficController.vhd(34)
Error (10028): Can't resolve multiple constant drivers for net "state.EAW_YELLOW" at TrafficController.vhd(34)
Error (10028): Can't resolve multiple constant drivers for net "state.RED_STATE" at TrafficController.vhd(34)

and
warnings
Info (10041): Inferred latch for "NS_COUNT[0]" at TrafficController.vhd(34)
Info (10041): Inferred latch for "NS_COUNT[1]" at TrafficController.vhd(34)
Info (10041): Inferred latch for "NS_COUNT[2]" at TrafficController.vhd(34)
Info (10041): Inferred latch for "state.RED_STATE" at TrafficController.vhd(34)
Info (10041): Inferred latch for "state.EAW_YELLOW" at TrafficController.vhd(34)
Info (10041): Inferred latch for "state.NAS_YELLOW" at TrafficController.vhd(34)
Info (10041): Inferred latch for "state.EMERGENCY" at TrafficController.vhd(34)
Info (10041): Inferred latch for "state.EastandWest" at TrafficController.vhd(34)
Info (10041): Inferred latch for "state.NorthandSouth" at TrafficController.vhd(34)
Info (10041): Inferred latch for "Where" at TrafficController.vhd(34)
Info (10041): Inferred latch for "REW" at TrafficController.vhd(34)

what is and inferred latch?

 

[joris]

You are assigning to State in the second process a few times, surely that's wrong (they should be replaced with assignments to NextState)

I think you should only list 'state' in the sensitivity list.

With Xilinx XST I get this warning on those signals:
"Latches may be generated from incomplete case or if statements."
It means that you must give a signal a new value in every possible path.

 

[joris]

You can avoid a lot of difficulties by redesigning the code,
when you have only one clock'ed process, you won't have latches inferred.
That way you also get rid of the state/nextstate juggling.

 

[snjsteve]

What is the best way to do a state machine my professor said this is the best way but i find it confusing ?

 

[joris]

I think the easiest design is using one process which is driven by a clock (and perhaps an asynchronous reset signal).