"when" assignments in process ?

Discussion in 'VHDL' started by Sylvain Munaut, Mar 3, 2006.

  1. Hi,


    When outside of a process, to test something I can write

    is_equal <= '1' when foo = bar else '0';

    but how to do the same in a process ?

    for now i must write

    if foo=bar then
    is_equal <= '1';
    else
    is_equal <= '0';
    end if;


    Which is a _lot_ longer ...

    It can be shortened with

    is_equal <= '0';
    if foo=bar then
    is_equal <= '1';
    end if;

    But it's still a lot longer ...



    Sylvain
    Sylvain Munaut, Mar 3, 2006
    #1
    1. Advertising

  2. Sylvain Munaut

    Ben Jones Guest

    "Sylvain Munaut" <com.246tNt@tnt> wrote in message
    news:44081dfc$0$1163$...
    > When outside of a process, to test something I can write
    > is_equal <= '1' when foo = bar else '0';
    > but how to do the same in a process ?


    -- In your package of useful functions:

    function btsl(x : boolean) return std_logic is
    -- btsl == Boolean To Standard Logic
    begin if x then return '1'; else return '0'; end if;
    end btsl;


    -- In your design code:

    process(...)
    begin

    is_equal <= btsl(foo=bar);

    end process;

    That is fairly short...

    -Ben-
    Ben Jones, Mar 3, 2006
    #2
    1. Advertising

  3. Indeed thanks !

    I don't yet have the "function" reflex in VHDL for that kind of things.


    Sylvain

    Ben Jones wrote:
    > "Sylvain Munaut" <com.246tNt@tnt> wrote in message
    > news:44081dfc$0$1163$...
    >
    >>When outside of a process, to test something I can write
    >>is_equal <= '1' when foo = bar else '0';
    >>but how to do the same in a process ?

    >
    >
    > -- In your package of useful functions:
    >
    > function btsl(x : boolean) return std_logic is
    > -- btsl == Boolean To Standard Logic
    > begin if x then return '1'; else return '0'; end if;
    > end btsl;
    >
    >
    > -- In your design code:
    >
    > process(...)
    > begin
    >
    > is_equal <= btsl(foo=bar);
    >
    > end process;
    >
    > That is fairly short...
    >
    > -Ben-
    >
    >
    Sylvain Munaut, Mar 3, 2006
    #3
  4. Sylvain Munaut

    Jim Lewis Guest

    Sylvain,
    This is due to be fixed in the next revision of
    VHDL. This revision will first be standardized by
    Accellera (the group working on the revisions) in
    July of 2006.

    Please let your vendor know that you want them to
    implement this.

    Best Regards,
    Jim


    > Hi,
    >
    >
    > When outside of a process, to test something I can write
    >
    > is_equal <= '1' when foo = bar else '0';
    >
    > but how to do the same in a process ?
    >
    > for now i must write
    >
    > if foo=bar then
    > is_equal <= '1';
    > else
    > is_equal <= '0';
    > end if;
    >
    >
    > Which is a _lot_ longer ...
    >
    > It can be shortened with
    >
    > is_equal <= '0';
    > if foo=bar then
    > is_equal <= '1';
    > end if;
    >
    > But it's still a lot longer ...
    >
    >
    >
    > Sylvain



    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis, Mar 3, 2006
    #4
  5. Sylvain Munaut

    Jim Lewis Guest

    Ben,
    This too is due to be fixed in the next revision of
    VHDL. This revision will first be standardized by
    Accellera (the group working on the revisions) in
    July of 2006.

    is_equal <= foo ?= bar ;

    in addition:

    Reg1Sel <= BlkSel and (Addr ?= REG1_ADDR_LOC) ;

    Please let your vendor know that you want them to
    implement this.

    Cheers,
    Jim

    > -- In your package of useful functions:
    >
    > function btsl(x : boolean) return std_logic is
    > -- btsl == Boolean To Standard Logic
    > begin if x then return '1'; else return '0'; end if;
    > end btsl;
    >
    >
    > -- In your design code:
    >
    > process(...)
    > begin
    >
    > is_equal <= btsl(foo=bar);
    >
    > end process;
    >
    > That is fairly short...
    >
    > -Ben-
    >
    >



    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis, Mar 3, 2006
    #5
  6. Hi Jim,
    I miss you a lot.

    How about the "orif" keyword problem? It has been 5 years since the
    problem was raised and you recommented.

    Weng
    Weng Tianxiang, Mar 8, 2006
    #6
  7. Weng Tianxiang wrote:

    > How about the "orif" keyword problem?


    ORIF will only be a *problem* for me if we have
    to repeat these discussions:

    http://groups.google.com/groups/search?q=vhdl "orif"

    > It has been 5 years since the
    > problem was raised and you recommented.


    Jim's last comment was July 31, 2005.
    Please write yourself a function and
    spare me the details.

    -- Mike Treseler
    Mike Treseler, Mar 8, 2006
    #7
  8. Jim's response on July 31, 2005 is:
    > Here is another point your committee should pay attention to:
    > sensitivity list!


    > Why don't you propose to change it?


    Already did. See the fast track proposals at:
    http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/proposals.html

    See FT-19.

    It has nothing to do with "orif" keyword. Two different topics.

    Weng
    Weng Tianxiang, Mar 9, 2006
    #8
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Neil Zanella
    Replies:
    2
    Views:
    979
    Neil Zanella
    Oct 26, 2003
  2. Nicolas Matringe
    Replies:
    9
    Views:
    720
    Mike Treseler
    Jun 14, 2004
  3. Gary Thorpe

    Using aggregates for assignments

    Gary Thorpe, Jun 14, 2004, in forum: VHDL
    Replies:
    4
    Views:
    692
  4. KJ
    Replies:
    4
    Views:
    676
  5. Andy
    Replies:
    3
    Views:
    551
    rickman
    Sep 11, 2012
Loading...

Share This Page