When Design Becomes Technology Specific ?

Discussion in 'VHDL' started by Bar Nash, Oct 6, 2008.

  1. Bar Nash

    Bar Nash Guest

    Hi

    When a design turns into technology specific ?

    At the GATE LEVEL stage ?

    At the NETLIST stage ?

    Thanks
    EC
    Bar Nash, Oct 6, 2008
    #1
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  2. Bar Nash

    Muzaffer Kal Guest

    On Mon, 6 Oct 2008 22:36:15 +0200, "Bar Nash"
    <> wrote:

    >Hi
    >
    >When a design turns into technology specific ?
    >
    >At the GATE LEVEL stage ?
    >
    >At the NETLIST stage ?
    >
    >Thanks
    >EC
    >


    I am not sure about your terminology is above but here is what happens
    (usually) during (ASIC) synthesis: The tool maps the RTL to its
    internal representation; depending on the tool this representation may
    involve primitive gates (flops, nand, nor etc) or it may also include
    architectural constructs like adders (which can be changed from ripple
    to cla etc. later). Then this netlist gets mapped to specific gates in
    your library without concern to driving strength initially (again this
    depends on the tool) at which point it becomes specific to your
    technology library; at this stage there is also a timing optimization
    before placement which can involve architectural selection (which type
    of adders to use, remap muxes etc). Then these gates are placed and
    sized/resized and timing optimized, buffered etc. After placement
    clock tree is synthesized and inserted and then the design routed.

    To answer your question more clearly the design becomes technology
    specific after it gets converted to internal representation and before
    first timing optimization is done. But even at that stage some tools
    don't use the actual gates from your library but from an abstract one
    generated from your library to enable them do resizing more optimally.
    In today RTL to GDS flows, the exact point where your design becomes
    technology specific is difficult to answer and probably irrelevant
    too.

    Muzaffer Kal
    http://www.dspia.com
    Muzaffer Kal, Oct 7, 2008
    #2
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  3. Bar Nash

    Bar Nash Guest

    Thank you very much
    Your answer made the subject clear .
    EC

    "Muzaffer Kal" <> ???
    ??????:...
    > On Mon, 6 Oct 2008 22:36:15 +0200, "Bar Nash"
    > <> wrote:
    >
    >>Hi
    >>
    >>When a design turns into technology specific ?
    >>
    >>At the GATE LEVEL stage ?
    >>
    >>At the NETLIST stage ?
    >>
    >>Thanks
    >>EC
    >>

    >
    > I am not sure about your terminology is above but here is what happens
    > (usually) during (ASIC) synthesis: The tool maps the RTL to its
    > internal representation; depending on the tool this representation may
    > involve primitive gates (flops, nand, nor etc) or it may also include
    > architectural constructs like adders (which can be changed from ripple
    > to cla etc. later). Then this netlist gets mapped to specific gates in
    > your library without concern to driving strength initially (again this
    > depends on the tool) at which point it becomes specific to your
    > technology library; at this stage there is also a timing optimization
    > before placement which can involve architectural selection (which type
    > of adders to use, remap muxes etc). Then these gates are placed and
    > sized/resized and timing optimized, buffered etc. After placement
    > clock tree is synthesized and inserted and then the design routed.
    >
    > To answer your question more clearly the design becomes technology
    > specific after it gets converted to internal representation and before
    > first timing optimization is done. But even at that stage some tools
    > don't use the actual gates from your library but from an abstract one
    > generated from your library to enable them do resizing more optimally.
    > In today RTL to GDS flows, the exact point where your design becomes
    > technology specific is difficult to answer and probably irrelevant
    > too.
    >
    > Muzaffer Kal
    > http://www.dspia.com
    Bar Nash, Oct 7, 2008
    #3
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