when sampled signal falling or rising edge

Discussion in 'VHDL' started by picnanard, Sep 1, 2008.

  1. picnanard

    picnanard

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    I have a very simple question? With a simple example:
    Inside same fpga. Inside one process I generate a signal wide one period on rising edge.
    If I want test this signal inside another process on same clock. I must do that on falling or rising edge?

    Excuse for this biginner questionÖ¾
     
    picnanard, Sep 1, 2008
    #1
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