where is the mistake?

[\(beta-\) Frank Nitzsche]

Hello @all,

this code here I copied is a part from my projekt and this part is for a
display like CGA. All ports or signals are only in this part used. The
problem:

p_clk_o, pdta_o, hsync_o : work fine.
vsync_o : give me lots of additional random pulses. This additional pulses
have a same duration like the hsync-period.

I tried it with lower XTAL, but exactly the same is doing.

The code:

.....
Port (
clk_i: in std_logic; --XTAL 40 MHz
rst_n_i: in std_logic; --/Reset von extern
p_clk_o: out std_logic; --Pixelclock = clk_i / 2 = 20 Mhz
hsync_o: out std_logic;
vsync_o: out std_logic;
pdta_o: out std_logic); --Pixeldata, in this posting not shown, but
work fine
end md_vram;

architecture md_vram_arch of md_vram is
constant SPALTEN: integer :=799; --800 (0..799) phys. Spalten (horizontal)
constant ZEILEN: integer :=495; --496 (0..495) phys. Zeilenanzahl.
(vertical)
constant HSYNCPOS: integer :=680; --Position Hsyncpuls
constant HSYNCDELAY: integer :=112; --Duration Hsyncpuls (counts of
p_clk-pulses)
constant VSYNCPOS: integer :=428; --Position Vsyncpuls
constant VSYNCDELAY: integer :=14; --Duration Vsyncpuls (counts of
Hsync-pulses)
signal h_cnt_s: std_logic_vector(9 downto 0);--pro Zeile 640 aus 800 pixel
sichtbar
signal v_cnt_s: std_logic_vector(8 downto 0);--pro Screen 400 aus 496
Zeilen sichtbar
signal p_clk_s: std_logic; --Pixeltakt
signal hsync_s: std_logic;
signal vsync_s: std_logic;
----------------------------------------------------------------------------
---------------
begin
--
Videogenerator--------------------------------------------------------------
------------
-- Pixeltakt p_clk_io= clk_i / 2
Pixeltakt:
process(rst_n_i, clk_i)
begin
if rst_n_i='0' then
p_clk_s<='0';
elsif falling_edge(clk_i) then
p_clk_s <= not p_clk_s;
end if;
end process Pixeltakt;
p_clk_o <= p_clk_s;

-- Spalten zaehlen und Generierung der zykl.
Hsync-Pulse ----------------------------------
Hsync:
process(rst_n_i, p_clk_s)
begin
if rst_n_i='0' then
h_cnt_s <= (others => '0');
elsif falling_edge(p_clk_s) then
if h_cnt_s = SPALTEN then
h_cnt_s <= (others => '0');
else
h_cnt_s <= h_cnt_s + 1;
end if;
end if;
end process hsync;
hsync_s <= '0' when (h_cnt_s > HSYNCPOS and h_cnt_s < (HSYNCPOS +
HSYNCDELAY)) else '1';
hsync_o <= hsync_s;

-- Zeilen zaehlen und Generierung der zykl.
Vsync-Pulse -----------------------------------
Vsync:
process(rst_n_i, hsync_s)
begin
if rst_n_i='0' then
v_cnt_s <= (others => '0');
elsif rising_edge(hsync_s) then
if v_cnt_s = ZEILEN then
v_cnt_s <= (others => '0');
else
v_cnt_s <= v_cnt_s + 1;
end if;
end if;
end process vsync;
vsync_s <= '0' when (v_cnt_s > VSYNCPOS and v_cnt_s < (VSYNCPOS +
VSYNCDELAY)) else '1';
vsync_o <= vsync_s;
....

Has anybody an idea?? Target is a Spartan (because 5V needed)

Thank - Frank

 

[Symon]

It might not work because of skew on the clocks p_clk_s and hsync_s. Read up
about synchronous design. Make your whole design synchronous to the input
clock clk_i. Generate enables for the other processes. Make sure that clk_i
goes through a global clock buffer.
But, the most likely reason is that vsync comes from a combinational
circuit. All the inputs to this circuit can change at the same time giving
you glitches. Make it so it comes from a flip-flop.
cheers, Syms.

 

[Ralf Hildebrandt]

p_clk_o, pdta_o, hsync_o : work fine.
vsync_o : give me lots of additional random pulses. This additional pulses
have a same duration like the hsync-period.

vsync_s <= '0' when (v_cnt_s > VSYNCPOS and v_cnt_s < (VSYNCPOS +
VSYNCDELAY)) else '1';

This line describes pure combinational logic. (2 subtractors and some gates)
Combinational logic may infer hazards. If you compare a vector, that is
output of a counter (v_cnt_s), hazards are very likely.

The normal solution of this problem is buffering the signal vsync_s.
("Flop it".) This infers an additional delay of one clock, so you have
to modify the comparators.

Ralf

 

[Alan]

Hello @all,

this code here I copied is a part from my projekt and this part is for a
display like CGA. All ports or signals are only in this part used. The
problem:

p_clk_o, pdta_o, hsync_o : work fine.

vsync_o : give me lots of additional random pulses. This additional pulses
have a same duration like the hsync-period.

I assume that this is not working when using the Spartan chip or do you
also get the same problem during simulation?.

My guess is that you are mistaken when you say that hsync_o is working
correctly.

How are you monitoring hsync_o? Are you using an oscilloscope? If so
have a very close look at the signal. I suspect that there are multiple
logic transitions, each much less than 1ns apart. There may appear as
very narrow 'spikes' during the horizontal pulse. The spikes in the
horizontal sync will coincide with the vertical sync changing.

end process hsync;
hsync_s <= '0' when (h_cnt_s > HSYNCPOS and h_cnt_s < >(HSYNCPOS +
HSYNCDELAY)) else '1';
hsync_o <= hsync_s;

This decode should be within the clocked process to stop the problem.
However even then the design would not be fully synchronous..

In real life the outputs registers forming your horizontal count are not
all changing at the same time. There will be a variation in clock to
output delay and different delays to the decode that you are performing.
The decode will not see a clean transition from one count to the next.

I would not be using three different clocks derived from each other in
the way you have used them. I recommend that you reconsider the design
approach and _only_ use the 40MHz clock for generating both horizontal
and vertical syncs..

 

[Alan]

This line describes pure combinational logic. (2 subtractors and some gates)
Combinational logic may infer hazards. If you compare a vector, that is
output of a counter (v_cnt_s), hazards are very likely.

The hsync has the same problem and that is being used as a clock for the
vsync process.