Which is the most beautiful and memorable hardware structure in aCPU?

Discussion in 'VHDL' started by Weng Tianxiang, Mar 29, 2010.

  1. Hi,
    From the first moment I learn how stack segment and stack pointer are
    used to link all subroutines in PC, I have been appreciating the
    hardware structure as I can and I think it is the the most beautiful
    and memorable hardware structure I have learn from the CPU structure.

    I want to know who invented the structure. Is an IBM engineer?

    And it is strange enough that after PC was created, no big new
    structure in CPU has ever invented. MESI protocol? No. Changing 1 core
    to 2 core, or even 8 cores is considered as a big invention? No.

    Oh, I forgot to mention the most important invention since then is the
    Mouse we use it every day.

    Any idea?

    Weng
    Weng Tianxiang, Mar 29, 2010
    #1
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  2. Weng Tianxiang

    Sandro Guest

    On Mar 29, 4:06 am, Weng Tianxiang <> wrote:
    > ...
    > From the first moment I learn how stack segment and stack pointer are
    > used to link all subroutines in PC, I have been appreciating the
    > hardware structure as I can and I think it is the the most beautiful
    > and memorable hardware structure I have learn from the CPU structure.
    > I want to know who invented the structure. Is an IBM engineer?
    > And it is strange enough that after PC was created, no big new
    > structure in CPU has ever invented. MESI protocol? No. Changing 1 core
    > to 2 core, or even 8 cores is considered as a big invention? No.
    > Oh, I forgot to mention the most important invention since then is the
    > Mouse we use it every day.
    > Any idea?
    > ...
    > Weng


    A little bit OT... anyway I think you mean the "von Neumann
    architecture" and
    the "Harvard architecture" both being maybe the most (but not the
    only)
    used CPU architectures.
    You can use as start point the followings:
    http://en.wikipedia.org/wiki/Von_Neumann_architecture
    http://en.wikipedia.org/wiki/Harvard_architecture

    Regards
    Sandro
    Sandro, Mar 29, 2010
    #2
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  3. Weng Tianxiang

    whygee Guest

    Re: Which is the most beautiful and memorable hardware structurein a CPU?

    Sandro wrote:
    > A little bit OT...

    Yes, this thread would better suit the comp.arch group.
    There are great CPU architecture specialists there :)

    > Regards
    > Sandro

    yg

    --
    http://ygdes.com / http://yasep.org
    whygee, Mar 29, 2010
    #3
  4. Weng Tianxiang

    jacko Guest

    I think it was a high level language feature first.

    Are you talking of indexed indirect addressing mode (reg+#immediate)
    or the link unlink instruction sets for setting the stack pointer?
    Would the 6502 8 bit micro (ZZ),Y mode count? Or are you more PDP-11?
    jacko, Mar 29, 2010
    #4
  5. Re: Which is the most beautiful and memorable hardware structure in a CPU?

    On Sun, 28 Mar 2010 19:06:23 -0700 (PDT), Weng Tianxiang wrote:

    >From the first moment I learn how stack segment and stack pointer are
    >used to link all subroutines in PC, I have been appreciating the
    >hardware structure as I can and I think it is the the most beautiful
    >and memorable hardware structure I have learn from the CPU structure.


    Aw, c'mon. Most of that is software - the only hardware
    requirements are the ability to copy a stack pointer
    to/from some other place, and the ability to construct an
    address that's offset from a register or memory value.

    For sheer luminous beauty, let's hear it for the PDP-8's
    JMS instruction...

    oh, maybe not. OK, second attempt. SPARC register windows.

    No? Don't like that? OK, the Transputer's tiny 3-register
    evaluation stack, with context switches permitted only at
    points where the stack is known to be empty. The
    21st century operating system wonks could REALLY learn
    something about lightweight elegance from that one.

    What about the whole idea of a stack? How cool is that,
    if you haven't seen it before?

    Set-associative cache?

    Sheesh, the field is so crowded with beautiful, genius-level
    ideas - but we're all so familiar with them that we don't
    see how hard it must have been to come up with them in
    the first place. Trying to single out just one is silly.

    >Oh, I forgot to mention the most important invention since then is the
    >Mouse we use it every day.


    Crap.

    Are you *really* trying to convince us that the mouse is
    more important, elegant, beautiful than...
    - convolution codes? and Shannon's theorem?
    - quadrature modulation?
    - Boolean algebra? Set theory?
    - The Fourier transform?
    - crystallography?
    - The Goldberg Variations?

    The kind of slavish technology-worship that your original
    question exemplifies is depressing and backward-looking;
    it leads us into relying on past achievements instead of
    being thrilled by what might be if only we keep questioning.
    It's the kind of thinking that should (but too often does
    not) give technologists and businessmen a bad reputation.

    We technologists are the 21st-century equivalent of the
    19th century ironfounders. We're exploiting the heroic
    achievements of the recent past to build the infrastructure
    that the future needs. We are facilitators, not visionaries.
    The next half-century belongs to the molecular biologists
    and geneticists, and we are merely there to help out with
    the menial work. Get a sense of proportion.
    --
    Jonathan Bromley
    Jonathan Bromley, Mar 29, 2010
    #5
  6. Weng Tianxiang

    whygee Guest

    Re: Which is the most beautiful and memorable hardware structurein a CPU?

    Jonathan Bromley wrote:
    > Crap.
    >
    > Are you *really* trying to convince us that the mouse is
    > more important, elegant, beautiful than...
    > - convolution codes? and Shannon's theorem?
    > - quadrature modulation?
    > - Boolean algebra? Set theory?
    > - The Fourier transform?
    > - crystallography?
    > - The Goldberg Variations?


    I'll add the Burrows-Wheeler transform which enables great compression
    and the Reed-Solomon method for forward error correction, used in so many places.
    I wish I could come up with something as mind-boggling AND useful.

    > The kind of slavish technology-worship that your original
    > question exemplifies is depressing and backward-looking;
    > it leads us into relying on past achievements instead of
    > being thrilled by what might be if only we keep questioning.
    > It's the kind of thinking that should (but too often does
    > not) give technologists and businessmen a bad reputation.

    he seems to be too young or too noob to understand that yet.
    Give him 10 or 20 years...

    > Get a sense of proportion.

    This comes with learning, and Internet is a great facilitator
    for this. And other less noble things, but so is the human nature...

    yg
    --
    http://ygdes.com / http://yasep.org
    whygee, Mar 30, 2010
    #6
  7. Weng Tianxiang

    MitchAlsup Guest

    The most memorable hardware structure is the vector indirect
    addressing mode.

    Mitch
    MitchAlsup, Mar 30, 2010
    #7
  8. On Mon, 29 Mar 2010 19:39:12 -0700, MitchAlsup wrote:

    > The most memorable hardware structure is the vector indirect addressing
    > mode.


    I had a soft spot for the 3D-matrix-stride post-modify addressing mode
    that the Motorola 56000 had, for a while. (The processor still has the
    mode, I'm no longer so sure it was a good idea...) Certainly memorable.

    Cheers,

    --
    Andrew
    Andrew Reilly, Mar 30, 2010
    #8
  9. Weng Tianxiang

    Guest

    In article <>,
    MitchAlsup <> wrote:
    >The most memorable hardware structure is the vector indirect
    >addressing mode.


    Yes. There were and are more bizarre ones, but they are Not Memorable
    (see Sellars and Yeatman).


    Regards,
    Nick Maclaren.
    , Mar 30, 2010
    #9
  10. On Mar 30, 10:38 am, wrote:

    > Yes.  There were and are more bizarre ones, but they are Not Memorable
    > (see Sellars and Yeatman).


    Ooooh, I like that. Always good to bring a bit of high culture
    into the discussion.

    It may be Memorable, hut was it a Good Thing?

    _Sellar_ and Yeatman, I think you'll find (without the trailing 's').

    Thanks for tickling a long-dormant and much cherished memory.
    --
    Jonathan Bromley
    Jonathan Bromley, Mar 30, 2010
    #10
  11. In article <hosgq9$h5m$>, says...
    >
    >In article

    <>,
    >MitchAlsup <> wrote:
    >>The most memorable hardware structure is the vector indirect
    >>addressing mode.

    >
    >Yes. There were and are more bizarre ones, but they are Not Memorable
    >(see Sellars and Yeatman).
    >
    >
    >Regards,
    >Nick Maclaren.


    I'll see your vector indirect mode, and add segment descriptors!

    (Really, is anything more compilcated than VALC?)
    (Unisys Clearpath Libra (MCP) systems)
    (aka. A series)

    - Tim
    Tim McCaffrey, Mar 30, 2010
    #11
  12. Weng Tianxiang

    Jason Zheng Guest

    Re: Which is the most beautiful and memorable hardware structure ina CPU?

    On Sun, 28 Mar 2010 19:06:23 -0700 (PDT)
    Weng Tianxiang <> wrote:

    <snip>

    > And it is strange enough that after PC was created, no big new
    > structure in CPU has ever invented. MESI protocol? No. Changing 1 core
    > to 2 core, or even 8 cores is considered as a big invention? No.


    My favorite is the Translation Look-aside Buffers (TLB), of course
    invented by the IBM engineers. You have to appreciate the way it sounds
    (and its irrelevance to its true purpose).
    Jason Zheng, Mar 30, 2010
    #12
  13. On Mar 30, 10:41 am, Jason Zheng <> wrote:
    > On Sun, 28 Mar 2010 19:06:23 -0700 (PDT)
    >
    > Weng Tianxiang <> wrote:
    >
    > <snip>
    >
    > > And it is strange enough that after PC was created, no big new
    > > structure in CPU has ever invented. MESI protocol? No. Changing 1 core
    > > to 2 core, or even 8 cores is considered as a big invention? No.

    >
    > My favorite is the Translation Look-aside Buffers (TLB), of course
    > invented by the IBM engineers. You have to appreciate the way it sounds
    > (and its irrelevance to its true purpose).


    Haha, some people don't appreciate stack segment and stack pointer.

    There two reasons I appreciate most:
    1. It is very simple;
    2. I handles all subroutine calls with prefect beauty for last 60
    years.

    3 years ago when I first read BW transform, I was in awe in such a way
    that made me to excitement for a week.

    But sadly I found that BW transform cannot get the high compression
    rate even though we don't pay attention on the time the transform
    needs.

    I joined compression group and found there were few discussions on the
    BW transform, the main reason is its not highest compression rate.

    Weng
    Weng Tianxiang, Mar 30, 2010
    #13
  14. Re: Which is the most beautiful and memorable hardware structure in a CPU?

    In comp.arch.fpga Jason Zheng <> wrote:
    (snip)

    > My favorite is the Translation Look-aside Buffers (TLB), of course
    > invented by the IBM engineers. You have to appreciate the way it sounds
    > (and its irrelevance to its true purpose).


    If you read the IBM description of virtual storage, you would
    first believe that it went to the segment and page tables for
    each reference. That would make everything three times slower,
    so there is the TLB to speed thing up. Always interesting to
    me is that the IBM name stuck, unlike many IBM names.
    (Data set, IPL, to name two.)

    The TLB is carefully documented by IBM, including the PTLB
    instruction. (Purge TLB.) On the other hand, IBM doesn't
    document much about the data and/or instruction cache, leaving
    that up to the implementations to get right. Also, regarding
    virtual storage, there is the STO (segment table origin) cache
    that is also not documented by the architecture, but needed
    to speed thing up in the case of multiple address spaces.

    -- glen
    glen herrmannsfeldt, Mar 30, 2010
    #14
  15. Re: Which is the most beautiful and memorable hardware structure in a CPU?

    In comp.arch.fpga "Andy \"Krazy\" Glew" <> wrote:
    > The two hardware datastructures supporting out of order execution:


    > Reservation stations.


    > And, less beautifully, the register renaming map.


    Both from the IBM 360/91, as far as I know.

    S/360 has only four floating point registers, so register
    renaming was pretty important for out-of-order execution.

    OK, how about imprecise interrupts?

    -- glen
    glen herrmannsfeldt, Mar 31, 2010
    #15
  16. Weng Tianxiang

    James Harris Guest

    On 29 Mar, 22:36, Jonathan Bromley <>
    wrote:

    ....

    > No?  Don't like that?  OK, the Transputer's tiny 3-register
    > evaluation stack, with context switches permitted only at
    > points where the stack is known to be empty.  The
    > 21st century operating system wonks could REALLY learn
    > something about lightweight elegance from that one.


    And from its one-byte instructions. Four-bit opcode and four-bit data
    fields lead to 29 of the most-used instructions taking just one byte
    and allowing for about 256 others to be encoded in two bytes (though
    some used more). All this made effective on a 32-bit machine in the
    1980s!

    Of course the stack and zero-operand addressing made such tiny
    encoding possible. These days a single stack would probably effect a
    dependency between instructions which did not need one. Perhaps today
    such would be built as many micro-cores.

    James
    James Harris, Mar 31, 2010
    #16
  17. Weng Tianxiang

    Guest

    Re: Which is the most beautiful and memorable hardware structure in a CPU?

    In article <houi8s$rdm$>,
    glen herrmannsfeldt <> wrote:
    >In comp.arch.fpga "Andy \"Krazy\" Glew" <> wrote:
    >> The two hardware datastructures supporting out of order execution:

    >
    >> Reservation stations.

    >
    >> And, less beautifully, the register renaming map.

    >
    >Both from the IBM 360/91, as far as I know.
    >
    >S/360 has only four floating point registers, so register
    >renaming was pretty important for out-of-order execution.
    >
    >OK, how about imprecise interrupts?


    Not a problem, until you try to resume after trapping them :)

    And the reason they were a problem was that they DID'T have a
    lot of data structure to support them ....

    I like them, as a design methodology, but only if integrated into
    a restartable code sequence design and/or NOT used for anything
    that might need resumption. E.g. one of the Alpha's most stupid
    mistakes was to try and merge them with the use of interrupts for
    supporting IEEE's edge cases. The 8087 was just plain idiotic.


    Regards,
    Nick Maclaren.
    , Mar 31, 2010
    #17
  18. Re: Which is the most beautiful and memorable hardware structure in a CPU?

    In comp.arch.fpga "Andy \"Krazy\" Glew" <> wrote:
    (snip)

    > I never really knew how the 360/91 did register renaming.
    > I don't think it used a RAM style map. I think it used CAMs.


    > I actually asked Tomasulo this, but he never really answered
    > the question.


    Never having had anyone to ask, but only read about it in books,
    that sounds about right.

    The explanation I have seen for the CDB, common data bus, was
    that results come out broadcast to all possible destinations.
    Those destinations expecting a result from that source accept it.
    Possible destinations are registers, reservation stations
    (for adders or mutliply/divide), or to be written to main memory.
    Sources are results from arithmetic units, or data read from
    (750 ns, 16 way interleaved) main memory.

    Among the not so obvious ones, if you store to memory and then
    refetch, register renaming will detect the same address is
    being used and go directly to the source. (No cache on the
    360/91, it originated on the 360/85.)

    -- glen
    glen herrmannsfeldt, Apr 1, 2010
    #18
  19. Weng Tianxiang

    MitchAlsup Guest

    On Apr 1, 1:07 pm, glen herrmannsfeldt <> wrote:
    > The explanation I have seen for the CDB, common data bus, was
    > that results come out broadcast to all possible destinations.


    Do you realize that the length of this bus and the number of
    destination nodes was one of the reasons the IBM machine topped out at
    60ns while the CDC machines topped out at 27.5ns and could deliver 4
    result (and one load) per cycle (as catch-up bandwidth).

    Mitch
    MitchAlsup, Apr 1, 2010
    #19
  20. Weng Tianxiang

    Robert Myers Guest

    On Apr 1, 10:05 pm, "Andy \"Krazy\" Glew" <>
    wrote:

    > Myself, I thought it was obvious.


    There's your problem right there, Andy. Everyone else will say:

    1. It's already been done (heard way too many times in this forum).

    2. It was obvious (emphasis on the past tense).

    People answering either (1) or (2) assume that everything that can be
    thought of is already in textbooks. That's how they got to where they
    are.

    Robert.
    Robert Myers, Apr 2, 2010
    #20
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