Which Verification Methodologies Are You Using?

Discussion in 'VHDL' started by harrytheasicguy@gmail.com, Feb 4, 2009.

  1. Guest

    , Feb 4, 2009
    #1
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  2. On 2009-02-04, <>
    wrote:

    |---------------------------------------------------------------------|
    |"I'm conducting a one line poll of functional verification |
    |methodologies being used today. If you'd like to participate, take a|
    |look at my blog post: |
    | |
    |http://theasicguy.com/2009/02/03/verification-methodology-poll |
    | |
    |or go directly to the poll: |
    | |
    |http://www.doodle.com/participation.html?pollId=u5ust5s73h8y9r62 |
    | |
    |Please vote only once. |
    | |
    |harry the ASIC guy (http://theASICguy.com)" |
    |---------------------------------------------------------------------|

    Many of the things listed on that Doodle webpage are not methodologies.
     
    Nicholas Paul Collin Gloucester, Feb 5, 2009
    #2
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