white noise generator

Discussion in 'VHDL' started by MNQ, Aug 3, 2004.

  1. MNQ

    MNQ Guest

    Hi All,

    I need to create a pseudo random binary bit stream to be output from a cpld
    in VHDL. I was thinking of creating a 32 or 33 bit register and loading it
    with a fixed value and rotating that. Does this sound doable as a random
    bit generator?
    Thanks

    Naveed
    MNQ, Aug 3, 2004
    #1
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  2. > Hi All,
    >
    > I need to create a pseudo random binary bit stream to be output from a cpld
    > in VHDL. I was thinking of creating a 32 or 33 bit register and loading it
    > with a fixed value and rotating that. Does this sound doable as a random
    > bit generator?
    > Thanks


    Search on google for a PRBS generator. That should do the trick. Quite simple to
    build also. Just your registers with some XOR ports... I sometimes like to use a
    thing like this as a counter :D.

    Jan
    Jan De Ceuster, Aug 3, 2004
    #2
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  3. MNQ wrote:



    > I need to create a pseudo random binary bit stream ...


    > I was thinking of creating a 32 or 33 bit register and loading it
    > with a fixed value and rotating that. Does this sound doable as a random
    > bit generator?


    A pseudo-random bit stream is a little bit more: It is based on a
    primitive and irreducible polynomial over the Galois Field of 2. In
    hardware it is nothing more than a vector, that is shifted, _but_ on
    certain position fed back via XOR gates.

    You simply have to find such a polynomial. Every book about
    pseudo-random singal processing contains some. But you can also take the
    polynomials from CRC generators - it is the same principle. If you
    search for CRC polynomials you will often find pictures of them, so it
    should be easy to model them in hardware.

    Ralf
    Ralf Hildebrandt, Aug 3, 2004
    #3
  4. Ralf Hildebrandt <> writes:

    > MNQ wrote:
    >
    >
    >
    >> I need to create a pseudo random binary bit stream ...

    >
    >> I was thinking of creating a 32 or 33 bit register and loading it
    >> with a fixed value and rotating that. Does this sound doable as a random
    >> bit generator?

    >
    > A pseudo-random bit stream is a little bit more: It is based on a
    > primitive and irreducible polynomial over the Galois Field of 2. In
    > hardware it is nothing more than a vector, that is shifted, _but_ on
    > certain position fed back via XOR gates.
    >
    > You simply have to find such a polynomial. Every book about
    > pseudo-random singal processing contains some. But you can also take
    > the polynomials from CRC generators - it is the same principle. If you
    > search for CRC polynomials you will often find pictures of them, so it
    > should be easy to model them in hardware.


    You can get a good list of polynomials from the online version of
    "Numerical Recipes": http://lib-www.lanl.gov/numerical/

    Regards,


    Kai
    Kai Harrekilde-Petersen, Aug 3, 2004
    #4
  5. "MNQ" <> wrote in message news:<cenlj0$e6k$>...
    > Hi All,
    >
    > I need to create a pseudo random binary bit stream to be output from a cpld
    > in VHDL. I was thinking of creating a 32 or 33 bit register and loading it
    > with a fixed value and rotating that. Does this sound doable as a random
    > bit generator?
    > Thanks
    >
    > Naveed


    Naveed,

    There is an excellent free VHDL package, "lfsrstd.vhd" on Ben Cohen's
    website:
    http://members.aol.com/vhdlcohen/vhdl/Models.html. This has
    everything you will need to generate a maximal length pseudorandom
    sequence using a linear feedback shift register (LFSR). Check it out.

    Charles
    Charles M. Elias, Aug 6, 2004
    #5
  6. MNQ

    MNQ Guest

    Thanks for the link Charles. I will take a look now.

    Also Thanks for everyone's help so far. It has been very much appreciated

    Naveed


    "Charles M. Elias" <> wrote in message
    news:...
    > "MNQ" <> wrote in message

    news:<cenlj0$e6k$>...
    > > Hi All,
    > >
    > > I need to create a pseudo random binary bit stream to be output from a

    cpld
    > > in VHDL. I was thinking of creating a 32 or 33 bit register and loading

    it
    > > with a fixed value and rotating that. Does this sound doable as a

    random
    > > bit generator?
    > > Thanks
    > >
    > > Naveed

    >
    > Naveed,
    >
    > There is an excellent free VHDL package, "lfsrstd.vhd" on Ben Cohen's
    > website:
    > http://members.aol.com/vhdlcohen/vhdl/Models.html. This has
    > everything you will need to generate a maximal length pseudorandom
    > sequence using a linear feedback shift register (LFSR). Check it out.
    >
    > Charles
    MNQ, Aug 9, 2004
    #6
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