why am i getting incompatible error

[MNQ]

Hi reader

I am trying to rotate a serial data stream in a 7 bit register but keep
getting the following error.
--------------------------------------------
Started process "Synthesize".
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file H:/naveed/test/rotate.vhd in Library work.
ERROR:HDLParsers:800 - H:/naveed/test/rotate.vhd Line 35. Type of temp is
incompatible with type of data_in.
-->
Total memory usage is 40216 kilobytes
Error: XST failed
Reason:
Completed process "Synthesize".
-------------------------------------------

Can anyone tell me where I am going wrong. As I have spent along time and
cannot figure it out. I have pasted the code below. I would be grateful
for any hep.

Thanks
Naveed






--**************************************************************************
*************
-- Project : Rotate register
-- Author : Naveed Qayyum
-- Date : 15th April 2004
-- Notes : Demonstration of the ror and rol function used to rotate the
serial data
-- received within the temp register.
--**************************************************************************
*************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rotate is
Port ( clock : in std_logic;
reset : in std_logic;
data_in : in std_logic);
end rotate;

architecture Behavioral of rotate is

signal temp : bit_vector (7 downto 0);

begin

rotate : process (clock, reset)
begin
if reset='1' then
temp <= "00000000";
elsif clock='1' and clock'event then
temp(0) <= data_in;
temp <= temp rol 1;
end if;
end process rotate;

end Behavioral;

 

[Ray Andraka]

change
signal temp : bit_vector (7 downto 0);
to
signal temp : std_logic_vector (7 downto 0);

a bit vector is made up of type bit, which is not the same as type std_logic.


Also,
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

are non-standard libraries (compilation is not defined by a standard, so there
are differences from compiler to compiler).

Instead use:

use ieee.numeric_std.all;

Hi reader

I am trying to rotate a serial data stream in a 7 bit register but keep
getting the following error.
--------------------------------------------
Started process "Synthesize".
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file H:/naveed/test/rotate.vhd in Library work.
ERROR:HDLParsers:800 - H:/naveed/test/rotate.vhd Line 35. Type of temp is
incompatible with type of data_in.
-->
Total memory usage is 40216 kilobytes
Error: XST failed
Reason:
Completed process "Synthesize".
-------------------------------------------

Can anyone tell me where I am going wrong. As I have spent along time and
cannot figure it out. I have pasted the code below. I would be grateful
for any hep.

Thanks
Naveed

--**************************************************************************
*************
-- Project : Rotate register
-- Author : Naveed Qayyum
-- Date : 15th April 2004
-- Notes : Demonstration of the ror and rol function used to rotate the
serial data
-- received within the temp register.
--**************************************************************************
*************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rotate is
Port ( clock : in std_logic;
reset : in std_logic;
data_in : in std_logic);
end rotate;

architecture Behavioral of rotate is

signal temp : bit_vector (7 downto 0);

begin

rotate : process (clock, reset)
begin
if reset='1' then
temp <= "00000000";
elsif clock='1' and clock'event then
temp(0) <= data_in;
temp <= temp rol 1;
end if;
end process rotate;

end Behavioral;

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email (e-mail address removed)
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[fe]

data_in : in std_logic);

signal temp : bit_vector (7 downto 0);
temp(0) <= data_in;

bit_vector is an array of bit

data_in : in std_logic);
signal temp : bit_vector (7 downto 0);
temp(0) <= to_bit(data_in);

or

data_in : in std_logic);
signal temp : std_logic_vector (7 downto 0);
temp(0) <= data_in;

or

data_in : in bit);
signal temp : bit_vector (7 downto 0);
temp(0) <= data_in;

regards
fe

 

[deep]

the compiler may not be supporting rol... you can do instead...
...
...
temp(0)<= data_in;
temp<= temp(6 downto 0) & temp(7);

...
...
hope this helps...

dk

 

[deep]

the compiler may not be supporting rol... you can do instead...
...
...
temp(0)<= data_in;
temp<= temp(6 downto 0) & temp(7);

...
...
hope this helps...

dk

 

[MNQ]

Hello everybody,

Thanks for all your help.

I dont think the ror or rol functions work in the xilinx's ISE 5.1.03i
version. I tried the method below and it worked for me.

I used the following method in the end to represent a 16 bit shift register.
Which is what I wanted in the end.

Thanks
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rotate is
Port ( clock : in std_logic;
reset : in std_logic;
data_in : in std_logic);
end rotate;

architecture Behavioral of rotate is

signal temp : std_logic_vector (15 downto 0);

begin

rotate : process (clock, reset, data_in)
begin
if reset='1' then
temp <= "0000000000000000";
elsif clock='1' and clock'event then
temp(15 downto 0) <= temp(14 downto 0) & data_in;
end if;
end process rotate;

end Behavioral;