Why do we hate variables?

[Nicolas Matringe]

Hi
I was thinking about the "new" (new to me at least) state machine
description Jonathan Bromley posted here 2 weeks ago and I was wondering
why nobody ever told me about it before.
I realized that I've always been told to be very careful with variables
and I ended with the idea that "using variables is bad". I've discussed
with some collegues and they appear to think so too.
What's gone wrong between VHDL designers and variables? Is it too much
software-like? Were variables unreliably handled by former synthesis tools?
I think about starting a "rehabilitate VHDL variables" campaign... ;o)

 

[Mike Treseler]

Hi
I was thinking about the "new" (new to me at least) state machine
description Jonathan Bromley posted here 2 weeks ago and I was wondering
why nobody ever told me about it before.

VHDL variables have been discussed many times
in this group and you can read all about them
in Ashenden's Designer's Guide.

Many hardware designers prefer to describe logic from
a schematic or a netlist point of view.
In a schematic, there is no concept of a local variable.
A wire labeled FOO on sheet one is always has the same
value as the wire FOO on sheet 47.

I realized that I've always been told to be very careful with variables
and I ended with the idea that "using variables is bad". I've discussed
with some collegues and they appear to think so too.

It is a normal reaction to be wary of the unknown.

What's gone wrong between VHDL designers and variables? Is it too much
software-like?

You only need VHDL variables if you value
algorithmic logic descriptions and clean
and concise code. Many logic designers don't,
and get by fine using all signals of type
std_logic_vector.

Were variables unreliably handled by former synthesis tools?

I don't know. I have never run into this, but
there are (and were) lots of tools out there.

I do know that quartus, leo, modelsim and sonata
handle variables just fine.

I think about starting a "rehabilitate VHDL variables" campaign... ;o)

Consider holding off on the campaign until you
have some successful designs to show off.
People will notice your elegant code and fast sims.

-- Mike Treseler

 

[Kai Harrekilde-Petersen]

VHDL variables have been discussed many times
in this group and you can read all about them
in Ashenden's Designer's Guide.

Many hardware designers prefer to describe logic from
a schematic or a netlist point of view.
In a schematic, there is no concept of a local variable.
A wire labeled FOO on sheet one is always has the same
value as the wire FOO on sheet 47.


It is a normal reaction to be wary of the unknown.


You only need VHDL variables if you value
algorithmic logic descriptions and clean
and concise code. Many logic designers don't,
and get by fine using all signals of type
std_logic_vector.


I don't know. I have never run into this, but
there are (and were) lots of tools out there.

I have friends who was badly burnt by "early" VHDL synthesis tools
that didn't understand that a variable could turn into an FF. I think
it was Autologic-II.

Consider holding off on the campaign until you
have some successful designs to show off.
People will notice your elegant code and fast sims.

We actively encourage the use of variables. As with all new
techniques, start small and work your way up in complexity as you get
more and more proficient in working with variables.

The coding style does take some learning to master, and those that
(inevitably!) will be looking at your code at some point have to go
through the same learning curve.


/Kai

 

[Jos De Laender]

Hi
I was thinking about the "new" (new to me at least) state machine
description Jonathan Bromley posted here 2 weeks ago and I was wondering
why nobody ever told me about it before.
I realized that I've always been told to be very careful with variables
and I ended with the idea that "using variables is bad". I've discussed
with some collegues and they appear to think so too.
What's gone wrong between VHDL designers and variables? Is it too much
software-like? Were variables unreliably handled by former synthesis
tools? I think about starting a "rehabilitate VHDL variables" campaign...
;o)

They simulate too fast, they don't occupy enough memory, they allow to write
algorithms too concise and too elegant , they degrade signals to
interprocess communication. That's why a lot of 'VHDL designers' do not
like them.

So I won't support your campaign ;-)

But more seriously : there's for the uncautious designer a slightly
increased risk on too long paths of logic. Not that it should per
construction , but I just observed ...

 

[fabbl]

My Two Cents:

I too am a hardware designer that looks at the design from a netlist point
of view to avoid synthesis problems. At the design level I avoid variables,
however at the bench level I use them more often and implement VHDL more as
a programing language. No predjudice, just like to make my design look like
a hardware (school of hard knocks!).

Thanks for the newsgroup, the descussions are very informative.