why does std_logic_arith suck?

Discussion in 'VHDL' started by Toby, Sep 7, 2005.

  1. Toby

    Toby Guest

    What are some specific problems with the std_logic_arith library? From
    what I am reading in these forums, it is better to use numeric_std, why
    exactly is it better? Any general answers on this issue would be
    great.

    Also, what I have been doing is simple arithmetic on std_logic_vectors
    (using std_logic_arith library). Sometimes it works and sometimes it
    doesnt. I understand that it is better to used signed or unsigned
    types for arithmetic operations and I am in the process of changing my
    code to do that, I am just trying to understand some of what I have
    seen. For example, for std_logic_vector signals A and B (using
    std_logic_arith), the following code seems to work in one part of my
    code, but the exact same code doesnt work if I put it in another part
    of the code:

    IF (A - B > 400) Then
    blah blah blah

    It seemed like if B was an input port (an actual entity input), it
    behaves differently than if B is a signal. Also seemed different if I
    put this line of code in a different process (i.e. everything wasn't
    concurrent like it is supposed to be). I dunno, anyone seen any
    wierdness like this?
     
    Toby, Sep 7, 2005
    #1
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  2. Toby wrote:

    > What are some specific problems with the std_logic_arith library?


    > Also, what I have been doing is simple arithmetic on std_logic_vectors

    ....

    This is one of the problems: How do you specify if these vectors are threatened as signed
    or unsigned data? (AFAIK it is done implicitely in this lirbary.)

    For some arithmetic operations it does not matter, but for a comparison it does.
    constant a : std_ulogic_vector:=16#ff#;
    constant b : std_ulogic_vector:=16#01#;
    Is a = 255 or a = -1 respectively is b greather than a or not?


    Ralf
     
    Ralf Hildebrandt, Sep 7, 2005
    #2
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  3. Toby wrote:
    > What are some specific problems with the std_logic_arith library?


    http://groups.google.com/groups?q=vhdl problems std_logic_arith numeric_std

    > It seemed like if B was an input port (an actual entity input), it
    > behaves differently than if B is a signal.


    An input port identifier must appear
    only on the right side of an assignment operator.

    A variable or signal identifier may appear
    on the left, right or both.
    Consider getting a vhdl simulator.

    -- Mike Treseler
     
    Mike Treseler, Sep 7, 2005
    #3
  4. Toby

    john Doef Guest

    Ralf Hildebrandt a écrit :
    > For some arithmetic operations it does not matter, but for a comparison it does.
    > constant a : std_ulogic_vector:=16#ff#;
    > constant b : std_ulogic_vector:=16#01#;
    > Is a = 255 or a = -1 respectively is b greather than a or not?

    Please, please,
    this is not correct vhdl.

    JD.
     
    john Doef, Sep 7, 2005
    #4
  5. john Doef wrote:

    > Ralf Hildebrandt a écrit :
    >>For some arithmetic operations it does not matter, but for a comparison it does.
    >>constant a : std_ulogic_vector:=16#ff#;
    >>constant b : std_ulogic_vector:=16#01#;
    >>Is a = 255 or a = -1 respectively is b greather than a or not?


    > Please, please,
    > this is not correct vhdl.
    > JD.


    Indeed a typo on the x"ff" and x"01"
    but Ralf's point to the OP is a good one.
    Using a plain std_logic_vector as an integer is ambiguous.

    -- Mike Treseler
     
    Mike Treseler, Sep 7, 2005
    #5
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