Why doesn't this situation generate a latch?

Discussion in 'VHDL' started by Weng Tianxiang, Mar 9, 2010.

  1. Hi,
    I have a question about when to generate a latch.

    In Example_1 and Exmaple_2, I don't think it will generate a latch. I
    don't know why.

    Example_1: process(RESET, CLK)
    Begin
    If RESET = ‘1’ then
    StateA <= S0;
    Elsif CLK’event = ‘1’ and CLK = ‘1’ then
    If SINI = ‘1’ then
    StateA <= S0;
    Elsif E2 = ‘1’ then
    null; -- missing a signal assignment statement
    -- I suppose it will not generate a latch, why?
    Elsif StateA = S1 then
    StateA <= S3;
    Else
    StateA <= StateA_NS;
    End if;
    End if;
    End process;

    Example_2: process(…)
    Begin
    Case StateA is
    ...; -- no signal assignement statements are missing
    End case;
    End process;

    Weng
    Weng Tianxiang, Mar 9, 2010
    #1
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  2. On Mar 8, 5:46 pm, Weng Tianxiang <> wrote:
    > Hi,
    > I have a question about when to generate a latch.
    >
    > In Example_1 and Exmaple_2, I don't think it will generate a latch. I
    > don't know why.
    >
    > Example_1: process(RESET, CLK)
    > Begin
    >         If RESET = ‘1’ then
    >                 StateA <= S0;
    >         Elsif CLK’event = ‘1’ and CLK = ‘1’ then
    >                 If SINI = ‘1’ then
    >                         StateA <= S0;
    >                 Elsif E2 = ‘1’ then
    >                         null;                   -- missing a signal assignment statement
    >                                                 -- I suppose it will not generate a latch, why?
    >                 Elsif StateA = S1 then
    >                         StateA <= S3;
    >                 Else
    >                         StateA <= StateA_NS;
    >                 End if;
    >         End if;
    > End process;
    >
    > Example_2: process(…)
    > Begin
    >         Case StateA is
    >                 ...;            -- no signal assignement statements are missing
    >         End case;
    > End process;
    >
    > Weng


    It doesn't generate a latch because you have fully defined a positive
    edge triggered register with an asynchronous reset.

    The result of the "Elsif E2 = '1' " comparison is that StateA remains
    the same as it was in the previous clk'event and this takes precedence
    over the next Elsif and Else statements.

    Ed McGettigan
    --
    Xilinx Inc.
    Ed McGettigan, Mar 9, 2010
    #2
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  3. Weng Tianxiang

    Tricky Guest

    On 9 Mar, 01:46, Weng Tianxiang <> wrote:
    > Hi,
    > I have a question about when to generate a latch.
    >
    > In Example_1 and Exmaple_2, I don't think it will generate a latch. I
    > don't know why.
    >
    > Example_1: process(RESET, CLK)
    > Begin
    >         If RESET = ‘1’ then
    >                 StateA <= S0;
    >         Elsif CLK’event = ‘1’ and CLK = ‘1’ then
    >                 If SINI = ‘1’ then
    >                         StateA <= S0;
    >                 Elsif E2 = ‘1’ then
    >                         null;                   -- missing a signal assignment statement
    >                                                 -- I suppose it will not generate a latch, why?
    >                 Elsif StateA = S1 then
    >                         StateA <= S3;
    >                 Else
    >                         StateA <= StateA_NS;
    >                 End if;
    >         End if;
    > End process;
    >
    > Example_2: process(…)
    > Begin
    >         Case StateA is
    >                 ...;            -- no signal assignement statements are missing
    >         End case;
    > End process;
    >
    > Weng


    In my mind, it generated a register with enable and async reset.
    Latches are only created when you dont have a clock in a process and
    you forget to assign something between process iterations.
    Tricky, Mar 9, 2010
    #3
  4. Weng Tianxiang

    Symon Guest

    On 3/9/2010 1:46 AM, Weng Tianxiang wrote:
    > Hi,
    > I have a question about when to generate a latch.
    >
    > In Example_1 and Exmaple_2, I don't think it will generate a latch. I
    > don't know why.
    >
    > Example_1: process(RESET, CLK)
    > Begin
    > If RESET = ‘1’ then
    > StateA<= S0;
    > Elsif CLK’event = ‘1’ and CLK = ‘1’ then
    > If SINI = ‘1’ then
    > StateA<= S0;
    > Elsif E2 = ‘1’ then
    > null; -- missing a signal assignment statement
    > -- I suppose it will not generate a latch, why?
    > Elsif StateA = S1 then
    > StateA<= S3;
    > Else
    > StateA<= StateA_NS;
    > End if;
    > End if;
    > End process;
    >
    > Example_2: process(…)
    > Begin
    > Case StateA is
    > ...; -- no signal assignement statements are missing
    > End case;
    > End process;
    >
    > Weng


    It will generate latches. Specifically, ones which are paired as master
    and slave.
    HTH., Syms.

    http://en.wikipedia.org/wiki/Flip-f....80.93slave_.28pulse-triggered.29_D_flip-flop
    Symon, Mar 9, 2010
    #4
  5. On Mar 9, 12:32 am, Tricky <> wrote:
    > On 9 Mar, 01:46, Weng Tianxiang <> wrote:
    >
    >
    >
    >
    >
    > > Hi,
    > > I have a question about when to generate a latch.

    >
    > > In Example_1 and Exmaple_2, I don't think it will generate a latch. I
    > > don't know why.

    >
    > > Example_1: process(RESET, CLK)
    > > Begin
    > >         If RESET = ‘1’ then
    > >                 StateA <= S0;
    > >         Elsif CLK’event = ‘1’ and CLK = ‘1’ then
    > >                 If SINI = ‘1’ then
    > >                         StateA <= S0;
    > >                 Elsif E2 = ‘1’ then
    > >                         null;                   -- missing a signal assignment statement
    > >                                                 -- I suppose it will not generate a latch, why?
    > >                 Elsif StateA = S1 then
    > >                         StateA <= S3;
    > >                 Else
    > >                         StateA <= StateA_NS;
    > >                 End if;
    > >         End if;
    > > End process;

    >
    > > Example_2: process(…)
    > > Begin
    > >         Case StateA is
    > >                 ...;            -- no signal assignement statements are missing
    > >         End case;
    > > End process;

    >
    > > Weng

    >
    > In my mind, it generated a register with enable and async reset.
    > Latches are only created when you dont have a clock in a process and
    > you forget to assign something between process iterations.


    Example_1: process(RESET, CLK)
    Begin
    If RESET = ‘1’ then
    StateA <= S0;
    Elsif CLK’event = ‘1’ and CLK = ‘1’ then
    If SINI = ‘1’ then
    StateA <= S0;
    Elsif E2 = ‘1’ then
    null; -- missing a signal assignment statement
    -- I suppose it will not generate a latch, why?
    Elsif StateA = S1 then
    StateA <= S3;
    Elsif C1 /= '1' then
    StateA <= StateA_NS;
    -- else -- missing a signal assignment statement
    -- null; -- I suppose it will not generate a latch, why?
    End if;
    End if;
    End process;

    Example_2: process(…)
    Begin
    Case StateA is
    ...; -- no signal assignement statements are missing
    End case;
    End process;

    Weng
    Weng Tianxiang, Mar 9, 2010
    #5
  6. On Mar 9, 7:24 am, Weng Tianxiang <> wrote:
    > On Mar 9, 12:32 am, Tricky <> wrote:
    >
    >
    >
    >
    >
    > > On 9 Mar, 01:46, Weng Tianxiang <> wrote:

    >
    > > > Hi,
    > > > I have a question about when to generate a latch.

    >
    > > > In Example_1 and Exmaple_2, I don't think it will generate a latch. I
    > > > don't know why.

    >
    > > > Example_1: process(RESET, CLK)
    > > > Begin
    > > >         If RESET = ‘1’ then
    > > >                 StateA <= S0;
    > > >         Elsif CLK’event = ‘1’ and CLK = ‘1’ then
    > > >                 If SINI = ‘1’ then
    > > >                         StateA <= S0;
    > > >                 Elsif E2 = ‘1’ then
    > > >                         null;                   -- missing a signal assignment statement
    > > >                                                 -- I suppose it will not generate a latch, why?
    > > >                 Elsif StateA = S1 then
    > > >                         StateA <= S3;
    > > >                 Else
    > > >                         StateA <= StateA_NS;
    > > >                 End if;
    > > >         End if;
    > > > End process;

    >
    > > > Example_2: process(…)
    > > > Begin
    > > >         Case StateA is
    > > >                 ...;            -- no signal assignement statements are missing
    > > >         End case;
    > > > End process;

    >
    > > > Weng

    >
    > > In my mind, it generated a register with enable and async reset.
    > > Latches are only created when you dont have a clock in a process and
    > > you forget to assign something between process iterations.

    >
    > Example_1: process(RESET, CLK)
    > Begin
    >    If RESET = ‘1’ then
    >       StateA <= S0;
    >    Elsif CLK’event = ‘1’ and CLK = ‘1’ then
    >       If SINI = ‘1’ then
    >          StateA <= S0;
    >       Elsif E2 = ‘1’ then
    >          null;    -- missing a signal assignment statement
    >                   -- I suppose it will not generate a latch, why?
    >       Elsif StateA = S1 then
    >          StateA <= S3;
    >       Elsif C1 /= '1' then
    >          StateA <= StateA_NS;
    >    -- else         -- missing a signal assignment statement
    >    --    null;     -- I suppose it will not generate a latch, why?
    >       End if;
    >    End if;
    > End process;
    >
    > Example_2: process(…)
    > Begin
    >    Case StateA is
    >       ...;            -- no signal assignement statements are missing
    >    End case;
    > End process;
    >
    > Weng- Hide quoted text -
    >
    > - Show quoted text -


    It isn't clear what you are looking for or trying learn with this code
    snippets. In both case these are the classical register coding
    styles.

    1) The process has two signals, RESET and CLK, in the sensitivity list
    2) There is only one signal, StateA, assignment
    3) The RESET is coded as an active high level asynchronous reset
    function
    Note: S0 should be a fixed static value or this will cause
    problems
    4) The CLK is coded as a rising edge clock and generates the register
    element.
    Note: Everything within this ELSIF statement is evaluated only on
    the rising edge

    I would strongly encourage you to change the RESET function from
    asynchronous to synchronous.

    Ed McGettigan
    --
    Xilinx Inc.
    Ed McGettigan, Mar 9, 2010
    #6
  7. On Mar 9, 10:15 am, Ed McGettigan <> wrote:
    > On Mar 9, 7:24 am, Weng Tianxiang <> wrote:
    >
    >
    >
    >
    >
    > > On Mar 9, 12:32 am, Tricky <> wrote:

    >
    > > > On 9 Mar, 01:46, Weng Tianxiang <> wrote:

    >
    > > > > Hi,
    > > > > I have a question about when to generate a latch.

    >
    > > > > In Example_1 and Exmaple_2, I don't think it will generate a latch. I
    > > > > don't know why.

    >
    > > > > Example_1: process(RESET, CLK)
    > > > > Begin
    > > > >         If RESET = ‘1’ then
    > > > >                 StateA <= S0;
    > > > >         Elsif CLK’event = ‘1’ and CLK = ‘1’ then
    > > > >                 If SINI = ‘1’ then
    > > > >                         StateA <= S0;
    > > > >                 Elsif E2 = ‘1’ then
    > > > >                         null;                   -- missing a signal assignment statement
    > > > >                                                 -- I suppose it will not generate a latch, why?
    > > > >                 Elsif StateA = S1 then
    > > > >                         StateA <= S3;
    > > > >                 Else
    > > > >                         StateA <= StateA_NS;
    > > > >                 End if;
    > > > >         End if;
    > > > > End process;

    >
    > > > > Example_2: process(…)
    > > > > Begin
    > > > >         Case StateA is
    > > > >                 ...;            -- no signal assignement statements are missing
    > > > >         End case;
    > > > > End process;

    >
    > > > > Weng

    >
    > > > In my mind, it generated a register with enable and async reset.
    > > > Latches are only created when you dont have a clock in a process and
    > > > you forget to assign something between process iterations.

    >
    > > Example_1: process(RESET, CLK)
    > > Begin
    > >    If RESET = ‘1’ then
    > >       StateA <= S0;
    > >    Elsif CLK’event = ‘1’ and CLK = ‘1’ then
    > >       If SINI = ‘1’ then
    > >          StateA <= S0;
    > >       Elsif E2 = ‘1’ then
    > >          null;    -- missing a signal assignment statement
    > >                   -- I suppose it will not generate a latch, why?
    > >       Elsif StateA = S1 then
    > >          StateA <= S3;
    > >       Elsif C1 /= '1' then
    > >          StateA <= StateA_NS;
    > >    -- else         -- missing a signal assignment statement
    > >    --    null;     -- I suppose it will not generate a latch, why?
    > >       End if;
    > >    End if;
    > > End process;

    >
    > > Example_2: process(…)
    > > Begin
    > >    Case StateA is
    > >       ...;            -- no signal assignement statements are missing
    > >    End case;
    > > End process;

    >
    > > Weng- Hide quoted text -

    >
    > > - Show quoted text -

    >
    > It isn't clear what you are looking for or trying learn with this code
    > snippets.  In both case these are the classical register coding
    > styles.
    >
    > 1) The process has two signals, RESET and CLK, in the sensitivity list
    > 2) There is only one signal, StateA, assignment
    > 3) The RESET is coded as an active high level asynchronous reset
    > function
    >      Note: S0 should be a fixed static value or this will cause
    > problems
    > 4) The CLK is coded as a rising edge clock and generates the register
    > element.
    >      Note: Everything within this ELSIF statement is evaluated only on
    > the rising edge
    >
    > I would strongly encourage you to change the RESET function from
    > asynchronous to synchronous.
    >
    > Ed McGettigan
    > --
    > Xilinx Inc.


    Ed,
    Thank you.

    Weng
    Weng Tianxiang, Mar 9, 2010
    #7
  8. Weng Tianxiang

    Andy Guest

    Weng,

    Let's look at what behavior generates a latch: The need for the
    circuit to remember a previous assignment from a previous execution of
    the process, when no other storage media is implied (i.e. in a
    combinatorial process). In a clocked process, the register does the
    remembering, since the process will have to remember the previous
    assignment when it executes on the falling edge too). A clock enable
    is added when the process must remember over more than one clock
    cycle.

    Looking at it another way, conceptually, a latch is nothing than a mux
    with feedback around whatever the input logic was (combinatorial). A
    register with clock enable is conceptually just a mux with feedback
    too, but the feedback is from the output of the register back to its
    input. So, in a combinatorial process with a missed assignment, you
    get a latch, whereas in a clocked process, it gets implemented with a
    clock enable on the register, and no latch is needed.

    Some synthesis tools may be getting smart enough to optimize an
    inferred latch from a combinatorial process into a clock enable on the
    corresponding register implied by the clocked process. But if there
    are any other combinatorial processes that use that latched output of
    the first combinatorial process, then the latch cannot be replaced by
    a clock enable on a register.

    Andy
    Andy, Mar 10, 2010
    #8
  9. Weng Tianxiang

    Andy Guest

    On Mar 9, 12:15 pm, Ed McGettigan <> wrote:
    > I would strongly encourage you to change the RESET function from
    > asynchronous to synchronous.


    On what basis do you make this recommendation, and what does this have
    to do with latches?

    Andy
    Andy, Mar 10, 2010
    #9
  10. Weng Tianxiang

    Peter Alfke Guest

    On Mar 10, 10:06 am, Andy <> wrote:
    > On Mar 9, 12:15 pm, Ed McGettigan <> wrote:
    >
    > > I would strongly encourage you to change the RESET function from
    > > asynchronous to synchronous.

    >
    > On what basis do you make this recommendation, and what does this have
    > to do with latches?
    >
    > Andy


    Please allow me to chime in with a basic tutorial:
    Latches and flip/flops=registers have common features and also a big
    difference:
    They both are storage elements, both have a Data input (D) and a data
    output ( Q), and both have a control input called Enable or Clock.
    (Let me ignore the contentious issue of asynchronous or synchronous
    Reset/clear or Preset)

    The big difference:
    A latch is transparent,( i.e. Q follows D, and thus there is no
    storage), whenever the Enable input is active. But Data is stored when
    Enable is inactive.
    A flip-flop is NEVER transparent. (D can never affect Q directly). Q
    assumes the state that D had right before the rising edge of the
    clock.

    How is this done?
    Inside the flip-flop, there are two cascaded latches (called Master
    and Slave).
    The Master latch is transparent and its internal output follows the D
    input as long as the Clock is low.
    The Slave latch is transparent and its external output Q follows the
    slave's internal output whenever the Clock is High, but during this
    time the Master is non-transparent = locked up.
    So the two cascaded latches have the opposite enable polarity.
    Thus the flip-flop's Q output can only change on (i.e. right after)
    the rising clock edge.

    I do not want to belabor the advantages of either design, just to
    avoid confusion.
    The flip-flop or register is the prevalent design. It wins the Oscar
    in most (but not all) cases..., but RAM cells always use the simpler
    latch structure.

    Peter Alfke, (teacher at heart)
    Peter Alfke, Mar 10, 2010
    #10
  11. In comp.arch.fpga Peter Alfke <> wrote:
    (snip)

    > I do not want to belabor the advantages of either design,
    > just to avoid confusion.


    > The flip-flop or register is the prevalent design. It wins the Oscar
    > in most (but not all) cases..., but RAM cells always use the simpler
    > latch structure.


    To be more specific, SRAM. Now, are there more SRAM cells around
    than registers bits in processors? If you count SRAM in processor
    cache memory it might be that there are more.

    For the first digital logic class I had, all the classroom
    demonstrations were done with paired RS flip-flops and
    a two phase clock. It does make it easier to understand in
    a classroom setting. Also, many past processors did use a
    two (or more) phase clock. (I remember stories about the
    four phase clock for the TMS9900.)

    It would be interesting to have an FPGA with transparent latches
    after each LUT instead of the current edge triggered FFs.

    -- glen
    glen herrmannsfeldt, Mar 10, 2010
    #11
  12. Weng Tianxiang

    Peter Alfke Guest

    On Mar 10, 12:08 pm, glen herrmannsfeldt <>
    wrote:
    >
    > It would be interesting to have an FPGA with transparent latches
    > after each LUT instead of the current edge triggered FFs.
    >
    > -- glen


    Glen, I simplified a little. I was frustrated by all the VHDL mumbo-
    jumbo.

    To answer your suggestion:
    Use Xilinx FPGAs. I know for sure that Virtex 5, and probably also 4
    and 6 can configure each flip-flop as a latch, although this is a
    rarely-used feature.
    (How fast I forget such exotic facts).
    Peter
    Peter Alfke, Mar 10, 2010
    #12
  13. In comp.arch.fpga Peter Alfke <> wrote:
    (snip)

    > To answer your suggestion:
    > Use Xilinx FPGAs. I know for sure that Virtex 5, and probably also 4
    > and 6 can configure each flip-flop as a latch, although this is a
    > rarely-used feature.
    > (How fast I forget such exotic facts).


    I didn't know that!

    There is discussion in another newsgroup about recreating the
    IBM 360/91 in an FPGA. I believe that is the machine that the
    Earle latch was invented for. (Maybe it was the Stretch.)

    The Earle latch pretty much takes one level of logic and combines
    it with the logic of a transparent latch. When every propagation
    delay counts, that helps a lot.

    -- glen
    glen herrmannsfeldt, Mar 10, 2010
    #13
  14. Weng Tianxiang

    Peter Alfke Guest

    On Mar 10, 12:31 pm, glen herrmannsfeldt <>
    wrote:
    > In comp.arch.fpga Peter Alfke <> wrote:
    > (snip)
    >
    > > To answer your suggestion:
    > > Use Xilinx FPGAs. I know for sure that Virtex 5, and probably also 4
    > > and 6 can configure each flip-flop as a latch, although this is a
    > > rarely-used feature.
    > > (How fast I forget such exotic facts).

    >
    > I didn't know that!  
    >
    > There is discussion in another newsgroup about recreating the
    > IBM 360/91 in an FPGA.  I believe that is the machine that the
    > Earle latch was invented for.  (Maybe it was the Stretch.)
    >
    > The Earle latch pretty much takes one level of logic and combines
    > it with the logic of a transparent latch.  When every propagation
    > delay counts, that helps a lot.  
    >
    > -- glen


    Glen: from the Virtex-6 User Guide Lite:
    The look-up tables (LUTs) in Virtex-6 FPGAs can be configured as
    either 6-input LUT (64-bit ROMs) with one output, or as two 5-input
    LUTs (32-bit ROMs) with separate outputs but common addresses or logic
    inputs. Each LUT output can optionally be registered in a flip-flop.
    Four such LUTs and their eight flip-flops as well as multiplexers and
    arithmetic carry logic form a slice, and two slices form a
    configurable logic block (CLB). Four flip-flops per slice (one per
    LUT) can optionally be configured as latches. In that case, the
    remaining four flip-flops in that slice must remain unused.

    So, that says it: 4 latches per slice. Perhaps not the highest
    efficiency, but not too bad.

    PS, I am very proud of these User Guides Lite, created and published
    as a bootleg project, but still very popular with users.
    Peter
    Peter Alfke, Mar 10, 2010
    #14
  15. Peter Alfke <> writes:

    > Use Xilinx FPGAs. I know for sure that Virtex 5, and probably also 4
    > and 6 can configure each flip-flop as a latch, although this is a
    > rarely-used feature.
    > (How fast I forget such exotic facts).


    And the Microblaze core uses 3 (yes a whole 3 :) of them as well!

    Martin

    --

    TRW Conekt - Consultancy in Engineering, Knowledge and Technology
    http://www.conekt.net/electronics.html
    Martin Thompson, Mar 11, 2010
    #15
    1. Advertising

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