why FSM so big

Discussion in 'VHDL' started by Pasacco, Jun 4, 2005.

  1. Pasacco

    Pasacco Guest

    Dear

    I implemented 12-state controller and the operations are basically

    ld 32bit data -> ld another 32bit data -> compare -> store into memory

    The operation above is repeated 1024 times.....

    Then I synthesized in FPGA tool.

    Problem is that the area is too big (more than 10% of Vertex2pro),
    though 'area' optimiation option was used.

    When I do the same thing with 128 times of ld/ld/cmp/store, the area
    was 3%.

    I am wondering why this happens....

    and I hope the area of FSM will be constant, regarless of the number of
    ld/st...

    If someone has this experience or idea, let me know....Thankyou
     
    Pasacco, Jun 4, 2005
    #1
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  2. Pasacco

    fred Guest

    In article <
    >, Pasacco <> writes
    >Dear
    >
    >I implemented 12-state controller and the operations are basically
    >
    >ld 32bit data -> ld another 32bit data -> compare -> store into memory
    >
    >The operation above is repeated 1024 times.....
    >
    >Then I synthesized in FPGA tool.
    >
    >Problem is that the area is too big (more than 10% of Vertex2pro),
    >though 'area' optimiation option was used.
    >
    >When I do the same thing with 128 times of ld/ld/cmp/store, the area
    >was 3%.


    Open the design in a physical editor (or look at the synth report) to see
    where the resources are being used and you will likely see where
    inefficiencies exist. Such an occurrence usually results from a difference in
    your understanding of how you think the design will implement and how the
    synthesis tool actually implements it. If you wish your design to share
    resources you must code in such a way that the synthesis tool has no
    choice but to operate (and share) in the way you intend it.

    You also make no mention of the size of your device.
    --
    fred
     
    fred, Jun 4, 2005
    #2
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  3. Pasacco

    mk Guest

    On 4 Jun 2005 11:09:34 -0700, "Pasacco" <> wrote:

    >Dear
    >
    >I implemented 12-state controller and the operations are basically
    >
    >ld 32bit data -> ld another 32bit data -> compare -> store into memory
    >
    >The operation above is repeated 1024 times.....
    >
    >Then I synthesized in FPGA tool.
    >
    >Problem is that the area is too big (more than 10% of Vertex2pro),
    >though 'area' optimiation option was used.
    >
    >When I do the same thing with 128 times of ld/ld/cmp/store, the area
    >was 3%.
    >
    >I am wondering why this happens....
    >
    >and I hope the area of FSM will be constant, regarless of the number of
    >ld/st...
    >
    >If someone has this experience or idea, let me know....Thankyou


    It seems you're somehow merging the your counter into your
    state-machine states. Without seeing your code, it would be difficult
    to point to what the problem is but what you can do is to instantiate
    a 10 bit counter and in a certain state of your FSM compare the
    counter value to your max count to decide whether to continue to load
    or terminate. This should decouple your FSM from the counter.
     
    mk, Jun 4, 2005
    #3
  4. Pasacco

    Pasacco Guest

    Hi

    Yes, it was 'counter' problem...when I removed it, the area is more or
    less same...
    Thankyou all for good comments
     
    Pasacco, Jun 5, 2005
    #4
  5. Pasacco

    Pasacco Guest

    Hi

    Yes, it was 'counter' problem...when I removed it, the area is more or
    less same...
    Thankyou all for good comments
     
    Pasacco, Jun 5, 2005
    #5
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