why "setup-time and hold-time"?

Discussion in 'VHDL' started by maazbecin, Jul 24, 2006.

  1. maazbecin

    maazbecin

    Joined:
    Jul 24, 2006
    Messages:
    1
    My name is Maaz,hello to every one!!!
    I am new member to this forum.Could anyone please clarify some doubts for me, on "setup time & hold time".

    I am aware of the fact that, setup time and hold time is necessary for the data to get sampled.ie., min time before the clk edge and after the clk edge.( a window , sort of thing) .These are the concepts, that are required.

    But, my questoins are,
    what is the necessity to have this window of setup time and hold time?

    also , these days, we have softcore processors like Nios II & microblaze, where in, they don't demand the data to be stable during Hold time, why is that!!!??.

    waiting for your replies
    kind regards
    Maaz
     
    maazbecin, Jul 24, 2006
    #1
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