Javier Castillo said:
Hello:
If you dont believe me ...
I do believe, that it is possible to write design in SystemC. There
may be some advantages of this approach for people with strong C
background. There are obviously drawbacks too, and I would like to
outline some of them.
1. Translation problems. I am really suspicious about "complete
automatization" of language translation process. The problem is to
make it work in ALL the cases. The easiest way to cleanup translation
may be to reduce "translatable" subset in SystemC. It may not be a
problem, but then it reduces "synthesizable" subset of SystemC and
converts it to even more limited subset of synthesizable Verilog RTL.
2. Descriptive power.
Verilog as a language was developed for RTL coding and constantly
improves during years of practice. For example, Verilog 2001 and then
SystemVerilog defines new useful constructs such as always_comb,
always_ff etc allowing designer to specify design intent in a way that
tools can verify. I doubt that SystemC has similar operator or can
produce them during code translation.
3. Need to maintain 2 code versions. Despite of Javier's opinion that
it is not a problem, I do see the need to maintain separately Verilog
version of RTL code. First, synthesis, STA and Equivalence checking
tools require verilog as an input. Then, there is a need to use
library cells, memories, DFT logic such as MBIST and JTAG, PLLs etc
etc. Do we have all this design infrastructure developed for SystemC?
4. Synthesis-STA-driven design modifications. These are very popular,
their intent is to improve timing performance of design. Translation
will complicate this process as well.
5. Maintenance effort. Designers cannot escape working and knowing
Verilog RTL. So they'll end up working with 2 languages as well as
constantly maintain functional equivalence between SystemC and Verilog
design representations.
In addition to design, I also doubt that SystemC is a good choise for
the whole verification environment. For the system-level verification,
it is a good choise since it allows seamless interoperability with the
software. For the functional verification, verification-specific
languages (HVL)or SystemVerilog would be much better choise.
Functional verification requires advanced coverage, random generation,
assertion support as well as may other items such as random stability
etc. I doubt that SystemC has similar capabilities comparing to HVLs
or SV.
Finally, there are already tools fo more efficient C-to-Verilog
integration than PLI provides. For example, VCS has DirectC interface.
Similar interface is also defined in SystemVerilog standard.
Regards,
Alexander Gnusin