Width issues in Synplify Pro 8.8

Discussion in 'VHDL' started by filmil, Jun 29, 2007.

  1. filmil

    filmil Guest

    Hello all.

    I am using Synplify Pro 8.8. Trying to synthesize a design I came
    across a vector width conflict I did not expect.

    During synthesis, Synplify Pro complains:
    CD 150: Width mismatch, variable foo has width 8, value 1.

    The unexpected part is that no widths should be equal to 1. Snippets
    follow.

    (in the architecture of top level module)
    component foo is
    generic ( ...
    bar : bit_vector(7 downto 0);
    ...);

    (somewhat later)
    foo_i : foo generic map ( bar => "00000000");

    Entity 'foo' is given as:

    entity foo is
    generic( bar : bit_vector := x"00");
    ...
    end;

    If I change the string "00000000" to "00000010" in the generic map for
    foo, I get no error. Likewise, b"00000000" instead of "00000000" gives
    no error. How can I get around this? That is, if I have a constant
    with predefined width, I would like the width to be honoured,
    irrespective of the actual value of the constant.

    For generics fixed through strings, I now know I can get away with
    putting b"0..0". But I have similar issues with initializers of the
    form (others => '0'), and int_to_bitvector(0,8). [int_to_bitvector is
    a function defined in a package I am using].

    Advice appreciated,
    f
    filmil, Jun 29, 2007
    #1
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