Will metastability not occur at the same clock domain?

[Tsun]

It is known that flip-flop has setup and hold time requirement for signal transition to happen properly. On the other hand, any violation of setup or hold time will cause metastability.

This is usually discussed in situation when a flip-flop is trying to register an asynchronous input, as discussed in the link below:

http://www.asic-world.com/tidbits/metastablity.html

It also suggests using cascaded flip-flops to prevent metastability to occur, according to the "So how do I avoid metastability?" section in the link above. In this case, Wouldn't metastability occur at the second flip-flop? Say at a rising clock edge, if fin(2) is going to change in delta time, it (as an input to the second flip-flop) may not fulfill the hold time and change too early so that the second flip-flop may not register it properly?

Therefore, shouldn't we use falling clock edge for the first flip-flop, and rising edge for the second flip-flop? So that fin(2) will not change when the second flip-flop is trying to read it?

 

[jeppe]

First of all - We like to concider Flop/Flops as digital components - But they are analoque inside and this leads to problems like metastability.

The metastabile state could be seen as logic "½" and even a bad Flip/Flips (in terms of MTBF) will not be able to clock a logic "½" from the D-input to Q.
The Q output bound to be either "0" or "1".

But if you wan't to be sure (for sure) then you could study the book "Digital Design Principles and Practice) by Wakerly.
In chapter 9, can will you find examples where the original Clk-frequency scaled down - in order to:
1) Reduce the times per second where metastability can occur.
2) Metastability will "die" after a few nano or microseconds and hence will the second Flip/Flop allways get a "good" signal.

This solutions will cost you a counter for downscaling + 2 F/F for the De-Meta-Chain and finaly one F/F in order to synchronize the final signal.