Will this "asynchronous handshaking" feasible in real circuits?

Discussion in 'VHDL' started by HUANG Huan, Feb 12, 2004.

  1. HUANG Huan

    HUANG Huan Guest

    "sig1" and "sig2" are two asynchronous signals. Both are low active.
    Assume that at any time the negative pulses of these two signals do
    not overlap and there is enough time between the two pulses.


    process (ack, sig1)
    begin
    if ack = '1' then
    ready <= '0';
    elsif rising_edge(sig1) then
    ready <= '1';
    end if;
    end process;

    process (ready, sig2)
    begin
    if ready = '0' then
    ack <= '0';
    elsif rising_edge(sig2) then
    ack <= '1';
    end if;
    end process;


    I use Xilinx FPGA to do the post-place-and-route simulation.
    The waveform is as follows:

    _______ _______________________________________
    | |
    sig1 |_____|

    __________________
    | |
    ready _______________| |_____________________

    ________________________ _________________________
    | |
    sig2 |_____|

    ___
    | |
    ack ________________________________| |___________________



    The pulse width of "ack" is about 4ns. Because the signal "ready" is
    actually a flip-flop and the signal "ack" is the asynchrounous reset
    of this flip-flop, will the pulse width of "ack" too short to clear
    the flip-flop in real circuits?


    Thank you!
     
    HUANG Huan, Feb 12, 2004
    #1
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  2. HUANG Huan

    VhdlCohen Guest

    >The pulse width of "ack" is about 4ns. Because the signal "ready" is
    >actually a flip-flop and the signal "ack" is the asynchrounous reset
    >of this flip-flop, will the pulse width of "ack" too short to clear
    >the flip-flop in real circuits?
    >


    Living dangerously! Speed is also a function of device lot, technology,
    temperature, voltage, and I doubt that you can guarantee performance thru all
    these variables.

    How about using clocks and reclocking critical signals to avoid metastability.

    On a scale of 1 to 5, where 5 is great, I would score that design a 1 because
    of reliability.
    -----------------------------------------------------------------------------
    Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
    http://www.vhdlcohen.com/
    Author of following textbooks:
    * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn
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    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
    ------------------------------------------------------------------------------
     
    VhdlCohen, Feb 13, 2004
    #2
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  3. HUANG Huan

    Dave Higton Guest

    In message <>
    (VhdlCohen) wrote:

    > >The pulse width of "ack" is about 4ns. Because the signal "ready" is
    > >actually a flip-flop and the signal "ack" is the asynchrounous reset
    > >of this flip-flop, will the pulse width of "ack" too short to clear
    > >the flip-flop in real circuits?
    > >

    >
    > Living dangerously! Speed is also a function of device lot, technology,
    > temperature, voltage, and I doubt that you can guarantee performance thru
    > all these variables.
    >
    > How about using clocks and reclocking critical signals to avoid
    > metastability.
    >
    > On a scale of 1 to 5, where 5 is great, I would score that design a 1
    > because of reliability.


    Sorry to come to this late; but I don't understand your objection.
    This is a causal system; ack can't go inactive again until ready has
    already gone to 0. I can't see how it could possibly fail. Propagation
    delay times make it /more/ secure.

    If ack were used to clear another flip-flop too, then I'd agree with
    you.

    Dave
     
    Dave Higton, Feb 24, 2004
    #3
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