Will this generate different HW?

Discussion in 'VHDL' started by Valentin Tihomirov, Oct 28, 2003.

  1. The question may a bit silly one but anyway... Assuming the process is
    synchronous.

    (a)

    Ack <= Loading;

    (b)

    if Loading = '1' then
    Ack <= '1';
    else
    Ack <= '0';
    end if;

    or the same

    Ack <= '0';
    if Loading = '1' then
    Ack <= '1';
    end if;


    The first should assign a signal directly while second assigns an output of
    a mux.
     
    Valentin Tihomirov, Oct 28, 2003
    #1
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  2. Valentin Tihomirov wrote:
    > The question may a bit silly one but anyway... Assuming the process is
    > synchronous.
    >
    > (a)
    >
    > Ack <= Loading;
    >
    > (b)
    >
    > if Loading = '1' then
    > Ack <= '1';
    > else
    > Ack <= '0';
    > end if;
    >
    > or the same
    >
    > Ack <= '0';
    > if Loading = '1' then
    > Ack <= '1';
    > end if;
    >
    >
    > The first should assign a signal directly while second assigns an output of
    > a mux.


    All three examples assign Ack with the value of
    Loading from the previous clock edge.

    I would expect synthesis to be the same in
    all three cases. Try it and see.

    For simulation,(b) zero's out H L and Z
    while (a) does not.

    -- Mike Treseler
     
    Mike Treseler, Oct 28, 2003
    #2
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  3. Valentin Tihomirov

    Mike Guest

    I would expect the last two statements to be minimized to the equivalent of
    the first one.


    "Valentin Tihomirov" <> wrote in message
    news:3f9e4e2f$...
    >
    > The question may a bit silly one but anyway... Assuming the process is
    > synchronous.
    >
    > (a)
    >
    > Ack <= Loading;
    >
    > (b)
    >
    > if Loading = '1' then
    > Ack <= '1';
    > else
    > Ack <= '0';
    > end if;
    >
    > or the same
    >
    > Ack <= '0';
    > if Loading = '1' then
    > Ack <= '1';
    > end if;
    >
    >
    > The first should assign a signal directly while second assigns an output

    of
    > a mux.
    >
    >
     
    Mike, Oct 28, 2003
    #3
  4. Mike Treseler wrote:
    > All three examples assign Ack with the value of
    > Loading from the previous clock edge.
    >
    > I would expect synthesis to be the same in
    > all three cases. Try it and see.
    >
    > For simulation,(b) zero's out H L and Z
    > while (a) does not.


    I guess this is the point: what are the data types of your
    signals? If it's BIT, then they might be the same.
    If they're STD_LOGIC, they behave differently and should
    thus generate different hardware.

    Lars
     
    Lars Wehmeyer, Oct 29, 2003
    #4
  5. What are the considerations to choose between the styles?
     
    Valentin Tihomirov, Oct 29, 2003
    #5
  6. Valentin Tihomirov wrote:
    > What are the considerations to choose between the styles?


    1. Easy to read and understand.
    2. Compatible with your tools.

    -- Mike Treseler
     
    Mike Treseler, Oct 29, 2003
    #6
  7. Lars Wehmeyer <> wrote:
    > Mike Treseler wrote:
    > > All three examples assign Ack with the value of
    > > Loading from the previous clock edge.

    [..]
    > > For simulation,(b) zero's out H L and Z
    > > while (a) does not.

    >
    > I guess this is the point: what are the data types of your
    > signals? If it's BIT, then they might be the same.
    > If they're STD_LOGIC, they behave differently and should
    > thus generate different hardware.


    No. The simulations may differ, but I expect no synthesis tool to
    produce different HW. Std_Logic differs from Bit only during
    simulations.

    bye Thomas
     
    Thomas Stanka, Nov 3, 2003
    #7
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