Wonder how to write the following code to be synthesizable

Discussion in 'VHDL' started by Stanley, Dec 7, 2004.

  1. Stanley

    Stanley Guest

    Hi all,
    I knew that my VHDL synthesizer "Synplify" does not support 2D array
    declaration...thus I wonder how can my input be rewritten into 1D
    array? Any feedback will be very appreciate!!!


    package test is
    type matrix is array(natural range<>, natural range<>) of complex;
    end package test;

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.math_real.all;
    use work.test.all;

    -- This matrix function calculates the square of each term, then
    returns the
    -- sum of sqared results
    -- This matrix function is capable to accept any length of matrix
    -- The data type can be either real or complex number (floating-point)


    entity matrix_agr is
    generic (args : integer :=1);
    port(
    arg: in matrix(0 to args, 0 to args);
    rst:in std_logic;
    result:eek:ut real
    );
    end matrix_agr;


    architecture beh of matrix_agr is


    begin

    process (rst) is
    variable temp_r,temp_i: real;

    begin

    if rst='1' then
    temp_r:=0.0;
    temp_i:=0.0;

    else
    for i in 0 to args loop
    for j in 0 to args loop
    temp_r:=temp_r + (arg(i,j).re)**2;
    temp_i:=temp_i + (arg(i,j).im)**2;

    end loop;
    end loop;

    end if;
    result<=temp_r + temp_i;

    end process;

    end architecture;
    Stanley, Dec 7, 2004
    #1
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  2. Stanley a écrit:
    > Hi all,
    > I knew that my VHDL synthesizer "Synplify" does not support 2D array
    > declaration...thus I wonder how can my input be rewritten into 1D
    > array? Any feedback will be very appreciate!!!
    >

    [...]

    > use ieee.math_real.all;
    > use work.test.all;


    math_real package is not synthesizable either.



    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
    Nicolas Matringe, Dec 7, 2004
    #2
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  3. Stanley

    Jim Lewis Guest

    Stanley,
    In the current revision of VHDL, passing matricies is
    difficult. In VHDL-2005, features are being added to fix
    this. However, if you really are only making one calculation
    per clock cycle, then you can greatly simplify your design.

    What you want to do is think of your matrix being stored
    in a ram or register bank in a separate block of your
    design. To initiate a matrix operation, have the storage
    block feed your design one value at a time. This means
    that your matrix calculation only needs to have the type
    complex (or two floating point values) as an input rather
    than having a matrix of these types.

    In the storage block you will need to create your memory.
    In your case a two dimensional array is appropriate, however,
    given the current state of synthesis tools, you will need to
    do this with arrays of arrays. Since this is entirely created
    in an architecture and the type will not need to be passed
    through an interface, you can use generics when you define
    the matrix type. The following takes a wack at your problem.

    type ComplexArray is array (natural range<>) of complex ;
    type ComplexMatrix is array (0 to args) of ComplexArray(0 to args) ;


    To access an element of an array of an array, you index it as
    follows:
    signal Matrix : ComplexMatrix ;
    signal Element : complex ;

    Element <= Matrix(1)(1) ; -- left index is the outermost array


    When you finish your storage block, submit it to your
    synthesis vendor and post it on the web. Tell them
    if they implemented two dimensional arrays that this
    type of problem would be easier for you. To get them
    to implement new features they need compelling examples
    and you probably have one. Be nice/professional about
    it as they have a right to earn a living too.


    As Nico mentioned, math_real is not synthesizable.
    For floating point, see the proposed IEEE floating
    point packages:
    http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html

    Two notes. First, these packages are proposals an may change
    before the final version is done. Second, I don't think
    anyone has create the type complex yet. You can create
    your own complex type or you pass in the re and im parts
    separately.

    You still have lots to fill in. Hopefully this points you in
    a good direction.


    If you want to define your own type complex the following
    is a wack at it:
    type complex is array(0 to 1) of fpxx ;

    where fpxx is a constrained floating point type.

    However, keep in mind that you will have to create your own
    functions for the type complex.

    In the next language revision (VHDL-2005), we should be
    able to create a more general type complex since we will
    not have to constrain the floating point type.

    Regards,
    Jim Lewis
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~




    > Hi all,
    > I knew that my VHDL synthesizer "Synplify" does not support 2D array
    > declaration...thus I wonder how can my input be rewritten into 1D
    > array? Any feedback will be very appreciate!!!
    >
    >
    > package test is
    > type matrix is array(natural range<>, natural range<>) of complex;
    > end package test;
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    > use ieee.numeric_std.all;
    > use ieee.math_real.all;
    > use work.test.all;
    >
    > -- This matrix function calculates the square of each term, then
    > returns the
    > -- sum of sqared results
    > -- This matrix function is capable to accept any length of matrix
    > -- The data type can be either real or complex number (floating-point)
    >
    >
    > entity matrix_agr is
    > generic (args : integer :=1);
    > port(
    > arg: in matrix(0 to args, 0 to args);
    > rst:in std_logic;
    > result:eek:ut real
    > );
    > end matrix_agr;
    >
    >
    > architecture beh of matrix_agr is
    >
    >
    > begin
    >
    > process (rst) is
    > variable temp_r,temp_i: real;
    >
    > begin
    >
    > if rst='1' then
    > temp_r:=0.0;
    > temp_i:=0.0;
    >
    > else
    > for i in 0 to args loop
    > for j in 0 to args loop
    > temp_r:=temp_r + (arg(i,j).re)**2;
    > temp_i:=temp_i + (arg(i,j).im)**2;
    >
    > end loop;
    > end loop;
    >
    > end if;
    > result<=temp_r + temp_i;
    >
    > end process;
    >
    > end architecture;
    Jim Lewis, Dec 7, 2004
    #3
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