Writing a binary output file

Discussion in 'VHDL' started by Fredxx, Sep 14, 2009.

  1. Fredxx

    Fredxx Guest

    I seem to be tying myself up in knots. I have written some VHDL to read
    from a binary file and this works fine.

    I'm now trying to write binary data to a file and would be grateful for a
    steer. I have looked at "write" and "writeline" but these seem to output
    bit to string conversions instead of a pure binary file.

    Would be grateful for some help.
    Fredxx, Sep 14, 2009
    #1
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  2. Fredxx wrote:

    > I'm now trying to write binary data to a file and would be grateful for a
    > steer. I have looked at "write" and "writeline" but these seem to output
    > bit to string conversions instead of a pure binary file.


    The un-overloaded write command makes binary files. See:

    http://mysite.verizon.net/miketreseler/char_file.vhd

    -- Mike Treseler
    Mike Treseler, Sep 14, 2009
    #2
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  3. Fredxx

    Fredxx Guest

    "Mike Treseler" <> wrote in message
    news:...
    > Fredxx wrote:
    >
    >> I'm now trying to write binary data to a file and would be grateful for a
    >> steer. I have looked at "write" and "writeline" but these seem to output
    >> bit to string conversions instead of a pure binary file.

    >
    > The un-overloaded write command makes binary files. See:
    >
    > http://mysite.verizon.net/miketreseler/char_file.vhd
    >


    I have come across this example, but I saw a constant array of characters so
    was a bit wary if it was relevant. I need to store std_logic_vector(7
    downto 0) to a file, or convert the std_logic_vector to a character. I was
    drawing a blank on this conversion as I need to store a byte on qualified
    clock cycles.

    Many thanks.
    Fredxx, Sep 14, 2009
    #3
  4. Fredxx wrote:

    >
    > I have come across this example, but I saw a constant array of characters so
    > was a bit wary if it was relevant.


    It is relevant to your question because modelsim happens to save vhdl
    characters as binary bytes. However this is not the safe or easy way to
    do what you want.

    Why not use 'write' to save the vhdl vector type you really want
    and let modelsim worry about the binary encoding and decoding.

    That way modelsim does the work instead of you.

    -- Mike Treseler
    Mike Treseler, Sep 14, 2009
    #4
  5. Fredxx

    Fredxx Guest

    "Mike Treseler" <> wrote in message
    news:...
    > Fredxx wrote:
    >
    >>
    >> I have come across this example, but I saw a constant array of characters
    >> so was a bit wary if it was relevant.

    >
    > It is relevant to your question because modelsim happens to save vhdl
    > characters as binary bytes. However this is not the safe or easy way to do
    > what you want.
    >
    > Why not use 'write' to save the vhdl vector type you really want
    > and let modelsim worry about the binary encoding and decoding.
    >
    > That way modelsim does the work instead of you.
    >


    write_file : process (Reset, Clock)
    subtype std_logic_vector_type is std_logic_vector(7 downto 0);
    type std_logic_vector_file is file of std_logic_vector_type;
    file myfile : std_logic_vector_file;

    begin
    if Reset = '1' then
    file_open ( myfile, "char_file.bin", write_mode);

    elsif Clock'event and Clock = '1' then
    write(myfile, Data);


    If I write a byte using say x"aa" the above, I get 8 bytes of hex in
    "char_file.bin"
    03 02 03 02 03 02 03 02

    I've tried various permutations but can't make any headway.

    Many thank, I wasn't aware you could have file types other than character.
    Fredxx, Sep 14, 2009
    #5
  6. Fredxx

    Fredxx Guest

    "Alan Fitch" <> wrote in message
    news:...
    > Fredxx wrote:
    >> "Mike Treseler" <> wrote in message
    >> news:...
    >>> Fredxx wrote:
    >>>
    >>>> I have come across this example, but I saw a constant array of
    >>>> characters so was a bit wary if it was relevant.
    >>> It is relevant to your question because modelsim happens to save vhdl
    >>> characters as binary bytes. However this is not the safe or easy way to
    >>> do what you want.
    >>>
    >>> Why not use 'write' to save the vhdl vector type you really want
    >>> and let modelsim worry about the binary encoding and decoding.
    >>>
    >>> That way modelsim does the work instead of you.
    >>>

    >>
    >> write_file : process (Reset, Clock)
    >> subtype std_logic_vector_type is std_logic_vector(7 downto 0);
    >> type std_logic_vector_file is file of std_logic_vector_type;
    >> file myfile : std_logic_vector_file;
    >>
    >> begin
    >> if Reset = '1' then
    >> file_open ( myfile, "char_file.bin", write_mode);
    >>
    >> elsif Clock'event and Clock = '1' then
    >> write(myfile, Data);
    >>
    >>
    >> If I write a byte using say x"aa" the above, I get 8 bytes of hex in
    >> "char_file.bin"
    >> 03 02 03 02 03 02 03 02
    >>
    >> I've tried various permutations but can't make any headway.
    >>

    > What do mean by "can't make any headway"?
    >
    > The output you show looks fine to me:
    >
    > std_logic_vector has 9 values
    >
    > 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-'
    >
    > so X"aa" is B"10101010" , '0' is at position 2 in the enumerated type and
    > 1 is at position 3, hence
    >
    > 3 2 3 2 3 2 3 2
    >
    > regards
    > Alan
    >


    Many thanks, I can now see where the output is of this form.

    What I'm trying to do is output the numeric value of a std_logic_vector(7
    downto 0) to a byte in a file.
    Fredxx, Sep 14, 2009
    #6
  7. Fredxx

    Fredxx Guest

    "Alan Fitch" <> wrote in message
    news:...
    > Fredxx wrote:
    >> "Alan Fitch" <> wrote in message
    >> news:...
    >>> Fredxx wrote:
    >>>> "Mike Treseler" <> wrote in message
    >>>> news:...
    >>>>> Fredxx wrote:
    >>>>>
    >>>>>> I have come across this example, but I saw a constant array of
    >>>>>> characters so was a bit wary if it was relevant.
    >>>>> It is relevant to your question because modelsim happens to save vhdl
    >>>>> characters as binary bytes. However this is not the safe or easy way
    >>>>> to do what you want.
    >>>>>
    >>>>> Why not use 'write' to save the vhdl vector type you really want
    >>>>> and let modelsim worry about the binary encoding and decoding.
    >>>>>
    >>>>> That way modelsim does the work instead of you.
    >>>>>
    >>>> write_file : process (Reset, Clock)
    >>>> subtype std_logic_vector_type is std_logic_vector(7 downto 0);
    >>>> type std_logic_vector_file is file of std_logic_vector_type;
    >>>> file myfile : std_logic_vector_file;
    >>>>
    >>>> begin
    >>>> if Reset = '1' then
    >>>> file_open ( myfile, "char_file.bin", write_mode);
    >>>>
    >>>> elsif Clock'event and Clock = '1' then
    >>>> write(myfile, Data);
    >>>>
    >>>>
    >>>> If I write a byte using say x"aa" the above, I get 8 bytes of hex in
    >>>> "char_file.bin"
    >>>> 03 02 03 02 03 02 03 02
    >>>>
    >>>> I've tried various permutations but can't make any headway.
    >>>>
    >>> What do mean by "can't make any headway"?
    >>>
    >>> The output you show looks fine to me:
    >>>
    >>> std_logic_vector has 9 values
    >>>
    >>> 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-'
    >>>
    >>> so X"aa" is B"10101010" , '0' is at position 2 in the enumerated type
    >>> and 1 is at position 3, hence
    >>>
    >>> 3 2 3 2 3 2 3 2
    >>>
    >>> regards
    >>> Alan
    >>>

    >>
    >> Many thanks, I can now see where the output is of this form.
    >>
    >> What I'm trying to do is output the numeric value of a std_logic_vector(7
    >> downto 0) to a byte in a file.
    >>
    >>

    >
    > In that case I agree with Mike, you need to open a file of character and
    > convert each binary value to an equivalent character. Of course you will
    > only be able to represent 0 and 1 (not X, Z and so on).
    >
    > Note that from VHDL 93 onwards, all 256 characters in the character set
    > are defined in the standard, so you can definitely store all 256 8 bit
    > values (VHDL 87 only had the first 128 characters if I remember correctly)
    >


    Many thanks again.

    I had come to that conclusion, my trouble which I haven't been able to
    overcome is converting std_logic_vector(7 downto 0) to a character. In the
    past I've used the likes of conv_integer and the like, and whilst I've
    googled and looked up in some reference files but I can't see a way of
    converting the value to a character.

    On the read side, there are more examples, and indeed I have a file read
    vhdl file which is working fine. But I can't seem to find any relevant
    examples on the write side.
    Fredxx, Sep 14, 2009
    #7
  8. Fredxx

    Fredxx Guest

    "Alan Fitch" <> wrote in message
    news:...
    > Fredxx wrote:
    >> "Alan Fitch" <> wrote in message
    >> news:...
    >>> Fredxx wrote:
    >>>> "Alan Fitch" <> wrote in message
    >>>> news:...
    >>>>> Fredxx wrote:
    >>>>>> "Mike Treseler" <> wrote in message

    >>
    >> I had come to that conclusion, my trouble which I haven't been able to
    >> overcome is converting std_logic_vector(7 downto 0) to a character. In
    >> the past I've used the likes of conv_integer and the like, and whilst
    >> I've googled and looked up in some reference files but I can't see a way
    >> of converting the value to a character.
    >>
    >> On the read side, there are more examples, and indeed I have a file read
    >> vhdl file which is working fine. But I can't seem to find any relevant
    >> examples on the write side.
    >>
    >>

    >
    > Hi Fred,
    > you'll need to convert to an integer, then to a character as follows (I
    > assume the use of ieee.numeric_std)
    >
    > process
    > variable s : std_logic_vector(7 downto 0);
    > variable c : CHARACTER;
    > begin
    > -- wait for clock etc
    > c := CHARACTER'VAL( to_integer(unsigned(s)) );
    >
    > 'VAL translates a position number to a value, 'POS translates a value to a
    > position number.
    >
    > It would be wise to check for metavalues, e.g.
    >
    > assert not is_X(s) report "meta-value in s";
    >
    > or something.
    >
    >


    Many thanks, much appreciated and it all works. I'm not very au fait with
    VAL or POS, and not many of the VHDL help pdf seem to mention them.
    Fredxx, Sep 14, 2009
    #8
  9. Mike Treseler, Sep 14, 2009
    #9
  10. Fredxx

    Fredxx Guest

    Fredxx, Sep 14, 2009
    #10
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