writing a makefile

[pereges]

This was a makefile written by a friend of mine using tcc as the
compiler. What would like to know is how are the makefiles written for
a different compiler (like say, gcc) would be different ?

# Makefile for project: AbsShell

CC=tcc

MODEL= -ml

COPTIONS= -c -C
LOPTIONS=

absshell.exe: absshell.obj abstools.obj abscmd.obj
$(CC) $(LOPTIONS) $(MODEL) absshell.obj abstools.obj abscmd.obj


absshell.h: absfunc.h
touch absshell.h

absshell.obj: absshell.h absshell.cpp
$(CC) $(COPTIONS) $(MODEL) absshell.cpp

abstools.obj: absshell.h abstools.cpp
$(CC) $(COPTIONS) $(MODEL) abstools.cpp

abscmd.obj: absshell.h abscmd.cpp
$(CC) $(COPTIONS) $(MODEL) abscmd.cpp


############################################################################

 

[Jens Thoms Toerring]

This was a makefile written by a friend of mine using tcc as the
compiler. What would like to know is how are the makefiles written for
a different compiler (like say, gcc) would be different ?

Sorry, but make files haven't anything to do with the compiler.
They are interpreted by the make program and not a compiler.
While the make program may invoke a C compiler in the process
(if a C program needs compiling) you can do lots of other things
with make files that don't need a C compiler at all.

CC=tcc

Just change this line to e.g.

CC=gcc

or whatever compiler you want to use.

COPTIONS= -c -C
LOPTIONS=

If necessary adjust these lines to the options the other
compiler (and linker) requires. I can't comment on this
any further since I don't know anything about tcc.

If you have further questions about make files you better ask
in e.g. comp.unix.programmer or, if this is a Windows specific
version of the make program, in some Windows newsgroup.

Regards, Jens

 

[Antoninus Twink]

This was a makefile written by a friend of mine using tcc as the
compiler. What would like to know is how are the makefiles written for
a different compiler (like say, gcc) would be different ?
[snip]
absshell.exe: absshell.obj abstools.obj abscmd.obj
$(CC) $(LOPTIONS) $(MODEL) absshell.obj abstools.obj abscmd.obj

This looks like a Windows setup, and it wouldn't surprise me if make for
Windows is no more sophisticated than the Windows shell, but as a
general rule you should try to use implicit built-in make rules wherever
possible, and only specify dependencies. For example, if you just
specifiy

absshell : absshell.o abstools.o abscmd.o

with no commands, then GNU make will automatically link this correctly as
$(CC) $(LDFLAGS) absshell.o abstools.o abscmd.o $(LOADLIBES) $(LDLIBS) -o absshell

Similarly it will make object files from .c files, etc.

Then you can change the C compiler used by modifying the $(CC) variable,
and add any compiler or linker flags you need to the standard $(CFLAGS)
etc. variables.