Writing Blockrams in VHDL

Discussion in 'VHDL' started by Mark van de Belt, Nov 13, 2003.

  1. Hello,

    I need to use a blockram as a FIFO to port data from one clock domain to
    another. I created a blockram with help of the language template. This
    blockram is recognised by the XST synthesiser. The dual clock is also
    recognised after a small modification. The next problem is to describe a
    databus width conversion. There is a 32 bit processor bus on one side and a
    1 bit serial output on the other side. This is no problem with a library
    element or a blockram instance from the coregen. I don't like the coregen
    modules because it is not easy to back-up your sources or transport them to
    another PC. The library instances make the code less portable. Is there a
    way to describe the width conversion in VHDL without creating extra logic
    outside of the blockram?

    Thanks,
    Mark


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    Mark van de Belt, Nov 13, 2003
    #1
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  2. Mark van de Belt

    Peter Alfke Guest

    Mark, I cannot help you with the VHDL, but recently having investigated
    a similar design, here are some issues:

    Asynchronous clocks mean that Empty and Full detection must cross the
    clock domain boundary, and simple comparators are bound to fail, unless
    you use Gray-coded addresses.
    The dual-width design, when going from narrow to wide, must deal with
    the issue of a partially assembled word still meaning "empty".
    All this becomes tricky at >200 MHz, but should be manageable at lower frequencies.
    Dual-clock FIFOs implemented in a dual-ported BlockRAM are trivial,
    until you have to detect Empty (Full is usually an avoidable situation
    that allows some cheating, but Empty can be tricky.)
    Peter Alfke

    Mark van de Belt wrote:
    >
    > Hello,
    >
    > I need to use a blockram as a FIFO to port data from one clock domain to
    > another. I created a blockram with help of the language template. This
    > blockram is recognised by the XST synthesiser. The dual clock is also
    > recognised after a small modification. The next problem is to describe a
    > databus width conversion. There is a 32 bit processor bus on one side and a
    > 1 bit serial output on the other side. This is no problem with a library
    > element or a blockram instance from the coregen. I don't like the coregen
    > modules because it is not easy to back-up your sources or transport them to
    > another PC. The library instances make the code less portable. Is there a
    > way to describe the width conversion in VHDL without creating extra logic
    > outside of the blockram?
    >
    > Thanks,
    > Mark
    >
    > ---
    > Outgoing mail is certified Virus Free.
    > Checked by AVG anti-virus system (http://www.grisoft.com).
    > Version: 6.0.538 / Virus Database: 333 - Release Date: 10-11-2003
    Peter Alfke, Nov 13, 2003
    #2
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  3. Thanks Peter for the warnings.
    We are building a FIFO with normal binary counters, but the empty and full
    signals are not based on bytes but on 64 byte packets. Therefore there is
    enough time to get a reliable empty and full indication in both clock
    domains. We also have the advantage that our clocks are 'slow' (40 - 50
    MHz). I have build these FIFO's with success before in other projects, but
    always with the aid of the core generator or library elements (the latter
    code is unreadable because 4 - 6 blockrams are instantiated for one
    blockram)

    Mark

    "Peter Alfke" <> schreef in bericht
    news:...
    > Mark, I cannot help you with the VHDL, but recently having investigated
    > a similar design, here are some issues:
    >
    > Asynchronous clocks mean that Empty and Full detection must cross the
    > clock domain boundary, and simple comparators are bound to fail, unless
    > you use Gray-coded addresses.
    > The dual-width design, when going from narrow to wide, must deal with
    > the issue of a partially assembled word still meaning "empty".
    > All this becomes tricky at >200 MHz, but should be manageable at lower

    frequencies.
    > Dual-clock FIFOs implemented in a dual-ported BlockRAM are trivial,
    > until you have to detect Empty (Full is usually an avoidable situation
    > that allows some cheating, but Empty can be tricky.)
    > Peter Alfke
    >
    > Mark van de Belt wrote:
    > >
    > > Hello,
    > >
    > > I need to use a blockram as a FIFO to port data from one clock domain to
    > > another. I created a blockram with help of the language template. This
    > > blockram is recognised by the XST synthesiser. The dual clock is also
    > > recognised after a small modification. The next problem is to describe a
    > > databus width conversion. There is a 32 bit processor bus on one side

    and a
    > > 1 bit serial output on the other side. This is no problem with a library
    > > element or a blockram instance from the coregen. I don't like the

    coregen
    > > modules because it is not easy to back-up your sources or transport them

    to
    > > another PC. The library instances make the code less portable. Is there

    a
    > > way to describe the width conversion in VHDL without creating extra

    logic
    > > outside of the blockram?
    > >
    > > Thanks,
    > > Mark
    > >
    > > ---
    > > Outgoing mail is certified Virus Free.
    > > Checked by AVG anti-virus system (http://www.grisoft.com).
    > > Version: 6.0.538 / Virus Database: 333 - Release Date: 10-11-2003



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    Mark van de Belt, Nov 14, 2003
    #3
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