Writing Test Bench

Discussion in 'VHDL' started by john, Mar 5, 2009.

  1. john

    john Guest

    HI,

    I interfaced a USB device with the FPGA. The USB device outputs 8 bit
    of parallel data at the falling edge of the USB_CLK. The 8 bit port
    that carries that Data is called " USB_Data". I am trying to write the
    VHDL Test Bench for this code, but no luck.

    The 8 bit data gets valid at least 10 ns before the falling edge of
    the USB_CLK. Please advice! I was also thinking that may be I can
    build a text file with binary numbers that I want to send to USB_CLK
    but I do not know how will it work or how can I do that using ISE
    10.1.

    The VHDL code and Test Bench are given below

    Thanks
    John


    My VHDL CODE :

    Library IEEE;
    USE IEEE.Std_logic_1164 .ALL;
    USE IEEE.Numeric_std .ALL;
    USE IEEE.STD_LOGIC_TEXTIO .ALL;
    --use ieee.numeric_bit.all;
    USE IEEE.std_logic_unsigned .all;

    Entity DPR_Writer is
    port (

    Data_Bus : out std_logic_vector (13 downto 0 );
    Address_bus : out std_logic_vector (18 downto 0 );
    Read_write : out std_logic;
    Output_Enable : out
    std_logic;
    CE0 : out std_logic;
    CE1 : out std_logic;
    LBL : out std_logic;
    UBL : out std_logic;
    USB_Data : in std_logic_vector (7 downto 0 );
    USB_CLK : in std_logic;
    ZZL : out std_logic:='0';
    SEML : out std_logic;
    OPTL : in std_logic;
    Reset : in std_logic;
    Indicator_LED : out std_logic;
    State_status : out std_logic_vector ( 1 downto 0)
    );
    End DPR_Writer;

    Architecture Writer of DPR_Writer is

    Signal State : std_logic_vector (1 downto 0);
    Signal Next_State : std_logic_vector(1 downto 0);
    Constant G0 :std_logic_vector (1 downto 0):="00";
    Constant G1 : std_logic_vector (1 downto 0):="01";
    Constant G2 : std_logic_vector (1 downto 0):="10";
    Constant G3 : std_logic_vector(1 downto 0):="11";
    Signal Incr : std_logic;
    Signal Stop : std_logic;
    Signal Counter : std_logic_vector ( 18 downto 0);
    Signal Ld_high : std_logic;
    Signal Ld_Low : std_logic;
    Signal Reset_out : std_logic;
    Signal incr_out : std_logic;
    Signal Ld_high_out : std_logic;
    Signal Ld_Low_out : std_logic;
    ------------------------------------

    Begin

    --CE0 <= '0';
    --CE1 <= '1';
    CE0 <= Ld_high;
    CE1 <= Ld_Low;
    Output_Enable <= '1';
    Read_write <= '0';
    SEML <=Reset_out;
    Address_bus <= Counter;
    ZZL <= incr ;
    State_status <= State;

    -------------------------------------

    State_Machine: Process (State)
    Begin
    Case State is

    When G0=>
    Ld_high <= '1';
    Ld_Low <= '0';
    --Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 );
    UBL <='0'; --1 old value
    LBL <='0'; --0 0ld value
    Next_State <=G1;
    -- Address Bus did not change

    When G1 =>
    Incr <='0';
    Ld_high <= '0';
    Ld_Low <= '1';
    --Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 );
    UBL <='0'; --0 old value
    LBL <='0'; --1 old value
    Next_State <=G2;
    -- Address Bus did not change

    When G2 =>
    Incr <='1';
    Ld_high <= '1';
    Ld_Low <= '0';
    --Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 );
    ---- Data_Bus ( 5 downto 0) <= USB_Data ( 5 downto 0 );
    UBL <='0';
    LBL <='0';
    Next_State <=G3;
    -- Address Bus changes

    When G3 =>
    Incr <='0';
    Ld_high <= '0';
    Ld_Low <= '1';
    --Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 );
    ---- Data_Bus ( 13 downto 6) <= USB_Data ( 7 downto 0 );
    UBL <='0';
    LBL <='0';
    Next_State <=G2;
    -- Address Bus did not change

    When others =>
    Next_State <=G0;
    End case;
    End Process;
    ----------------------------------------
    FSM : Process (USB_CLK,Reset_out)
    Begin

    If ( Reset_out= '1' ) Then
    Indicator_LED <= '1';
    State <= G0;
    elsIf (USB_CLK 'Event And USB_CLK = '1')Then
    Indicator_LED <= '0';
    State <= Next_State;
    End If;

    End Process;
    ----------------------------------------
    Count: Process ( USB_CLK,Reset_out, incr)
    Begin
    If ( Reset_out= '1' ) Then
    Counter <= (others => '0');

    elsif (USB_CLK 'Event And USB_CLK = '1')Then
    If ( Counter = 255008 )Then
    -- Counter will stop counting --
    elsif ( Incr = '1') then
    Counter <= Counter + 1;
    else
    Counter <= Counter;
    End if;
    End if;
    End Process;
    ----------------------------------------
    Data_Bus_Load: Process( USB_CLK, Ld_high, Ld_Low,Reset_out,USB_Data)
    Begin

    If ( Reset_out= '1' ) Then
    Data_Bus ( 13 downto 8) <=(others =>'0');
    Data_Bus ( 7 downto 0) <=(others =>'0');

    elsif (USB_CLK = '1')Then

    If ( Ld_high = '1' ) Then
    Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 );
    elsif (Ld_Low ='1') then
    Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 );
    elsif ( Ld_high = '0' ) Then
    elsif(Ld_Low ='0') then
    else
    end if;

    else
    end if;

    End Process;
    ----------------------------------------
    Reset_Scheme : Process( USB_CLK, Reset)
    variable Reset_in : std_logic;
    variable Reset_out_1 :std_logic;
    Begin
    If ( Reset = '1') then
    Reset_in := '1';
    Reset_out_1 := '1';
    Elsif rising_edge ( USB_CLK ) then
    Reset_out_1 := Reset_in;
    Reset_in :='0';
    End if ;
    Reset_out <= Reset_out_1;
    End Process;

    VHDL TEST BENCH
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.all;
    --USE ieee.numeric_std.ALL;
    USE IEEE.STD_LOGIC_TEXTIO .ALL;
    use ieee.numeric_bit.all;

    ENTITY ABC_TEST IS
    END ABC_TEST;

    ARCHITECTURE behavior OF ABC_TEST IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT DPR_Writer
    PORT(

    Data_Bus : OUT std_logic_vector (13 downto 0);
    Address_bus : OUT std_logic_vector (18 downto 0);
    Read_write : OUT std_logic;
    Output_Enable : OUT std_logic;
    CE0 : OUT std_logic;
    CE1 : OUT std_logic;
    LBL : OUT std_logic;
    UBL : OUT std_logic;
    USB_Data : IN std_logic_vector (7 downto 0);
    USB_CLK : IN std_logic;
    ZZL : OUT std_logic;
    SEML : OUT std_logic;
    OPTL : IN std_logic;
    Reset : IN std_logic;
    Indicator_LED : OUT std_logic;
    State_status : out std_logic_vector ( 1 downto 0)
    );
    END COMPONENT;


    --Inputs
    signal USB_Data :std_logic_vector (7 downto 0) := (others => '0');
    signal USB_CLK : std_logic := '0';
    signal OPTL : std_logic := '0';
    signal Reset : std_logic := '0';

    --Outputs
    signal Data_Bus : std_logic_vector (13 downto 0);
    signal Address_bus : std_logic_vector (18 downto 0);
    signal Read_write : std_logic;
    signal Output_Enable : std_logic;
    signal CE0 : std_logic;
    signal CE1 : std_logic;
    signal LBL : std_logic;
    signal UBL : std_logic;
    signal ZZL : std_logic;
    signal SEML : std_logic;
    signal Indicator_LED : std_logic;
    signal State_status : std_logic_vector ( 1 downto 0);
    constant USB_CLK_period : time := 42 ns;

    BEGIN
    -- Instantiate the Unit Under Test (UUT)
    uut: DPR_Writer PORT MAP (
    Data_Bus => Data_Bus,
    Address_bus => Address_bus,
    Read_write => Read_write,
    Output_Enable => Output_Enable,
    CE0 => CE0,
    CE1 => CE1,
    LBL => LBL,
    UBL => UBL,
    USB_Data => USB_Data,
    USB_CLK => USB_CLK,
    ZZL => ZZL,
    SEML => SEML,
    OPTL => OPTL,
    Reset => Reset,
    Indicator_LED => Indicator_LED,
    State_status => State_status
    );

    -------------------------------------------------
    USB_CLK_process :process
    begin
    USB_CLK<= '0';
    wait for USB_CLK_period/2;
    USB_CLK <= '1';
    wait for USB_CLK_period/2;
    end process;
    -----------------------------------------------

    -- Stimulus process
    stim_proc: process
    begin
    -- hold reset state for 100ms.
    wait for 100ms;
    wait for USB_CLK_period*10;
    -- insert stimulus here
    wait;
    end process;

    -------------------------------------------------

    Reset_Process: Process
    Begin
    Reset <= '1';
    wait for 100 ns;
    Reset <='0';
    wait for 6000 ns;
    End Process;

    -----------------------------------------------
    USB_Data_Stream: Process
    Begin

    wait on USB_CLK;
    USB_Data(0)<= '1' after 10ns;
    USB_Data(1)<='0' after 10ns;
    USB_Data(2)<= '1' after 10ns;
    USB_Data(3)<= '0' after 10ns;
    USB_Data(4)<= '1' after 10ns;
    USB_Data(5)<= '0' after 10ns;
    USB_Data(6)<= '1' after 10ns;
    USB_Data(7)<= '0' after 10ns;


    end process;
    ---------------------------------------------
    END behavior;
    john, Mar 5, 2009
    #1
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  2. john

    Guest

    Hi John
    You wrote: The USB device outputs 8 bit
    of parallel data at the falling edge of the USB_CLK.

    So, if you are using this clock for your FSM it should also use the
    falling clock edge in all processes.

    elsIf (USB_CLK 'Event And USB_CLK = '0')Then

    or

    elsif falling_edge(USB_CLK) then


    One more thing:
    What is it with this strange Data_Bus_Load Process??
    Why are you building latches using:

    elsif (USB_CLK = '1')Then

    This process seems to be some crap to replace the data multiplexor
    scheme in your FSM.
    Well, the multiplexor there would work, but where are the registers to
    store the data?
    (State_Machine is a combinatorical process!)
    Also you will get a wrong simulation of that process, because the
    Input USB_Data is not in the sensitivity list.
    (I know, the lines are commented out now. But before that?)

    Rethink your approach and clean up your code.

    Have a nice synthesis
    Eilert
    , Mar 6, 2009
    #2
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