X=T * AT '

Discussion in 'VHDL' started by VHDL_HELP, Mar 27, 2007.

  1. VHDL_HELP

    VHDL_HELP Guest

    Hi , my problem is to make a correct relation between my component to
    get a top module that calculate X=T * AT ' which T and AT are
    matrix :
    this is what i did :
    1: a module that calculate AT '
    2 : a module that calculate Y * Z
    3 : a module that can read the elements of AT ' given

    as a result , i cant get my correct result :
    please help me :

    --------- It is the top level
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity produit is
    Port ( clk : in STD_LOGIC;
    reset : in std_logic;
    at : in STD_LOGIC_VECTOR (2 downto 0);
    t : in STD_LOGIC_VECTOR (2 downto 0);
    clk_out : out STD_LOGIC;
    eat:eek:ut STD_LOGIC_VECTOR (2 downto 0);
    et:eek:ut STD_LOGIC_VECTOR (2 downto 0);
    pr : out STD_LOGIC_VECTOR (7 downto 0)
    );
    end produit;

    architecture Behavioral of produit is
    component changement_matrice
    port(clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    a : in STD_LOGIC_VECTOR (2 downto 0);
    clk_out:eek:ut std_logic;
    at : out STD_LOGIC_VECTOR (2 downto 0)
    );
    end component;
    component lecture_element
    Port ( clk : in STD_LOGIC;
    ae : in STD_LOGIC_VECTOR (2 downto 0);
    clk_out:eek:ut std_logic;
    el : out STD_LOGIC_VECTOR (2 downto 0)
    );
    end component;
    component produit_matrice is
    Port ( clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    at : in STD_LOGIC_VECTOR (2 downto 0);
    t : in STD_LOGIC_VECTOR (2 downto 0);
    clk_out : out STD_LOGIC;
    d : out STD_LOGIC_VECTOR (7 downto 0)
    );
    end component;
    signal clk_temp,clk_syn,clk_v:std_logic;
    signal at_tr,at_tr_lu:std_logic_vector(2 downto 0);
    begin
    G1:changement_matrice port map(clk,reset,at,clk_temp,at_tr);
    G2:lecture_element port map(clk_temp,at_tr,clk_syn,at_tr_lu);
    G3:produit_matrice port map(clk_syn,reset,t,at_tr_lu,clk_out,pr);
    end Behavioral;

    ----------------------------------------------------- It is the
    component to calculate the transpose
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity changement_matrice is
    Port ( clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    a : in STD_LOGIC_VECTOR (2 downto 0);
    clk_out:eek:ut std_logic ;
    at : out STD_LOGIC_VECTOR (2 downto 0) :
    );
    end changement_matrice;

    architecture Behavioral of changement_matrice is
    -- Tableau de 4 éléments des coeficients A et des 4 éléments de sortie
    de transposé
    type tab is array (3 downto 0) of std_logic_vector(2 downto 0);
    signal ta,tat:tab;
    begin
    process
    begin
    seq: loop
    -- Lecture de la matrice --
    WAIT UNTIL clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '1';
    ta(0) <= a;
    WAIT UNTIL clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '0';
    ta(1) <= a;
    WAIT UNTIL clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '1';
    ta(2) <= a;
    WAIT UNTIL clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '0';
    ta(3) <= a;
    -- Affectation de la transposé --
    WAIT UNTIL clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '1';
    at <= ta(0);
    WAIT UNTIL clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '0';
    at <= ta(2);
    WAIT UNTIL clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '1';
    at <= ta(1);
    WAIT UNTIL clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '0';
    clk_ver <= '1';
    at <= ta(3);
    END LOOP;
    end process;
    end Behavioral;
    ------------------------------------------- It is the component to
    make synchronisation to read elements transpose
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity lecture_element is
    Port ( clk : in STD_LOGIC;
    ae : in STD_LOGIC_VECTOR (2 downto 0);
    clk_out:eek:ut std_logic;
    el : out STD_LOGIC_VECTOR (2 downto 0));
    end lecture_element;

    architecture Behavioral of lecture_element is

    begin
    process(clk)
    begin
    if rising_edge(clk) then
    el <= ae;
    clk_out <= clk;
    end if;
    end process;
    end Behavioral;
    ----------------------------------- It is the component to make the
    multiplication
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity produit_matrice is
    Port ( clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    at : in STD_LOGIC_VECTOR (2 downto 0);
    t : in STD_LOGIC_VECTOR (2 downto 0);
    clk_out : out STD_LOGIC :='0';
    d : out STD_LOGIC_VECTOR (7 downto 0));
    end produit_matrice;

    architecture Behavioral of produit_matrice is
    -- Tableau de 16 éléments des coeficients A et I
    type tab is array (3 downto 0) of std_logic_vector(2 downto 0);
    -- Tableau des 8 éléments de produits
    type tabpr is array(7 downto 0)of std_logic_vector(5 downto 0);
    -- Tableau des éléments des additions
    type tabadd is array(3 downto 0) of std_logic_vector(7 downto 0);
    signal ta,tt:tab;
    signal tpr:tabpr;
    signal c:tabadd;
    begin
    process
    BEGIN
    seq:loop
    wait until clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '1';
    ta(0) <= at;
    tt(0) <= t;

    wait until clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '0';
    ta(1) <= at;
    tt(1) <= t;
    -- calcul de a1*b1
    tpr(0) <= ta(0) * tt(0);
    wait until clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '1';
    ta(2) <= at;
    tt(2) <= t;
    -- calcul a1*b2
    tpr(1) <= ta(0) * tt(1);
    wait until clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '0';
    ta(3) <= at;
    tt(3) <= t;
    -- calcul a2b3,a3b1,a3b2
    tpr(2) <= ta(1) * tt(2);
    tpr(3) <= ta(2) * tt(0);
    tpr(4) <= ta(2) * tt(1);

    wait until clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '1';
    -- calcul a2b4,a4b4,a4b3
    tpr(5) <= ta(1) * tt(3);
    tpr(6) <= ta(3) * tt(2);
    tpr(7) <= ta(3) * tt(3);
    -- Calcul des sommes ( produit des matrices
    wait until clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '0';
    c(0) <= "00" & tpr(0) + tpr(2);
    c(1) <= "00" & tpr(1) + tpr(5);
    c(2) <= "00" & tpr(3) + tpr(6);
    c(3) <= "00" & tpr(4) + tpr(7);

    wait until clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '1';
    d <= c(0);

    wait until clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '0';
    d <= c(1);

    wait until clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '1';
    d <= c(2);

    wait until clk'event and clk = '1';
    exit seq when reset = '1';
    clk_out <= '0';
    d <= c(3);
    end loop;
    end process;
    end Behavioral;

    -------------------------------------------
    Thank you for your help , all my respect
    VHDL_HELP, Mar 27, 2007
    #1
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  2. VHDL_HELP

    Jim Lewis Guest

    Dear FRIEND,
    I have been wondering all along why your professor is still
    using the non-standard packages:
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    Now I have a theory, it is so he/she can track your posts
    more easily. Then at the end of the class give you the
    portion of your grade that you actually accomplished (vs
    what was done for you here).

    :)

    P.S.
    It would be more polite to use a name than VHDL_HELP.

    > Hi , my problem is to make a correct relation between my component to
    > get a top module that calculate X=T * AT ' which T and AT are
    > matrix :
    > this is what i did :
    > 1: a module that calculate AT '
    > 2 : a module that calculate Y * Z
    > 3 : a module that can read the elements of AT ' given
    >
    > as a result , i cant get my correct result :
    > please help me :
    >
    > --------- It is the top level
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    > entity produit is
    > Port ( clk : in STD_LOGIC;
    > reset : in std_logic;
    > at : in STD_LOGIC_VECTOR (2 downto 0);
    > t : in STD_LOGIC_VECTOR (2 downto 0);
    > clk_out : out STD_LOGIC;
    > eat:eek:ut STD_LOGIC_VECTOR (2 downto 0);
    > et:eek:ut STD_LOGIC_VECTOR (2 downto 0);
    > pr : out STD_LOGIC_VECTOR (7 downto 0)
    > );
    > end produit;
    >
    > architecture Behavioral of produit is
    > component changement_matrice
    > port(clk : in STD_LOGIC;
    > reset : in STD_LOGIC;
    > a : in STD_LOGIC_VECTOR (2 downto 0);
    > clk_out:eek:ut std_logic;
    > at : out STD_LOGIC_VECTOR (2 downto 0)
    > );
    > end component;
    > component lecture_element
    > Port ( clk : in STD_LOGIC;
    > ae : in STD_LOGIC_VECTOR (2 downto 0);
    > clk_out:eek:ut std_logic;
    > el : out STD_LOGIC_VECTOR (2 downto 0)
    > );
    > end component;
    > component produit_matrice is
    > Port ( clk : in STD_LOGIC;
    > reset : in STD_LOGIC;
    > at : in STD_LOGIC_VECTOR (2 downto 0);
    > t : in STD_LOGIC_VECTOR (2 downto 0);
    > clk_out : out STD_LOGIC;
    > d : out STD_LOGIC_VECTOR (7 downto 0)
    > );
    > end component;
    > signal clk_temp,clk_syn,clk_v:std_logic;
    > signal at_tr,at_tr_lu:std_logic_vector(2 downto 0);
    > begin
    > G1:changement_matrice port map(clk,reset,at,clk_temp,at_tr);
    > G2:lecture_element port map(clk_temp,at_tr,clk_syn,at_tr_lu);
    > G3:produit_matrice port map(clk_syn,reset,t,at_tr_lu,clk_out,pr);
    > end Behavioral;
    >
    > ----------------------------------------------------- It is the
    > component to calculate the transpose
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    > entity changement_matrice is
    > Port ( clk : in STD_LOGIC;
    > reset : in STD_LOGIC;
    > a : in STD_LOGIC_VECTOR (2 downto 0);
    > clk_out:eek:ut std_logic ;
    > at : out STD_LOGIC_VECTOR (2 downto 0) :
    > );
    > end changement_matrice;
    >
    > architecture Behavioral of changement_matrice is
    > -- Tableau de 4 éléments des coeficients A et des 4 éléments de sortie
    > de transposé
    > type tab is array (3 downto 0) of std_logic_vector(2 downto 0);
    > signal ta,tat:tab;
    > begin
    > process
    > begin
    > seq: loop
    > -- Lecture de la matrice --
    > WAIT UNTIL clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '1';
    > ta(0) <= a;
    > WAIT UNTIL clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '0';
    > ta(1) <= a;
    > WAIT UNTIL clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '1';
    > ta(2) <= a;
    > WAIT UNTIL clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '0';
    > ta(3) <= a;
    > -- Affectation de la transposé --
    > WAIT UNTIL clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '1';
    > at <= ta(0);
    > WAIT UNTIL clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '0';
    > at <= ta(2);
    > WAIT UNTIL clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '1';
    > at <= ta(1);
    > WAIT UNTIL clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '0';
    > clk_ver <= '1';
    > at <= ta(3);
    > END LOOP;
    > end process;
    > end Behavioral;
    > ------------------------------------------- It is the component to
    > make synchronisation to read elements transpose
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    > entity lecture_element is
    > Port ( clk : in STD_LOGIC;
    > ae : in STD_LOGIC_VECTOR (2 downto 0);
    > clk_out:eek:ut std_logic;
    > el : out STD_LOGIC_VECTOR (2 downto 0));
    > end lecture_element;
    >
    > architecture Behavioral of lecture_element is
    >
    > begin
    > process(clk)
    > begin
    > if rising_edge(clk) then
    > el <= ae;
    > clk_out <= clk;
    > end if;
    > end process;
    > end Behavioral;
    > ----------------------------------- It is the component to make the
    > multiplication
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    > entity produit_matrice is
    > Port ( clk : in STD_LOGIC;
    > reset : in STD_LOGIC;
    > at : in STD_LOGIC_VECTOR (2 downto 0);
    > t : in STD_LOGIC_VECTOR (2 downto 0);
    > clk_out : out STD_LOGIC :='0';
    > d : out STD_LOGIC_VECTOR (7 downto 0));
    > end produit_matrice;
    >
    > architecture Behavioral of produit_matrice is
    > -- Tableau de 16 éléments des coeficients A et I
    > type tab is array (3 downto 0) of std_logic_vector(2 downto 0);
    > -- Tableau des 8 éléments de produits
    > type tabpr is array(7 downto 0)of std_logic_vector(5 downto 0);
    > -- Tableau des éléments des additions
    > type tabadd is array(3 downto 0) of std_logic_vector(7 downto 0);
    > signal ta,tt:tab;
    > signal tpr:tabpr;
    > signal c:tabadd;
    > begin
    > process
    > BEGIN
    > seq:loop
    > wait until clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '1';
    > ta(0) <= at;
    > tt(0) <= t;
    >
    > wait until clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '0';
    > ta(1) <= at;
    > tt(1) <= t;
    > -- calcul de a1*b1
    > tpr(0) <= ta(0) * tt(0);
    > wait until clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '1';
    > ta(2) <= at;
    > tt(2) <= t;
    > -- calcul a1*b2
    > tpr(1) <= ta(0) * tt(1);
    > wait until clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '0';
    > ta(3) <= at;
    > tt(3) <= t;
    > -- calcul a2b3,a3b1,a3b2
    > tpr(2) <= ta(1) * tt(2);
    > tpr(3) <= ta(2) * tt(0);
    > tpr(4) <= ta(2) * tt(1);
    >
    > wait until clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '1';
    > -- calcul a2b4,a4b4,a4b3
    > tpr(5) <= ta(1) * tt(3);
    > tpr(6) <= ta(3) * tt(2);
    > tpr(7) <= ta(3) * tt(3);
    > -- Calcul des sommes ( produit des matrices
    > wait until clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '0';
    > c(0) <= "00" & tpr(0) + tpr(2);
    > c(1) <= "00" & tpr(1) + tpr(5);
    > c(2) <= "00" & tpr(3) + tpr(6);
    > c(3) <= "00" & tpr(4) + tpr(7);
    >
    > wait until clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '1';
    > d <= c(0);
    >
    > wait until clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '0';
    > d <= c(1);
    >
    > wait until clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '1';
    > d <= c(2);
    >
    > wait until clk'event and clk = '1';
    > exit seq when reset = '1';
    > clk_out <= '0';
    > d <= c(3);
    > end loop;
    > end process;
    > end Behavioral;
    >
    > -------------------------------------------
    > Thank you for your help , all my respect
    >
    Jim Lewis, Mar 27, 2007
    #2
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  3. VHDL_HELP

    Guest

    hi

    what an horrible vhdl description !!!

    why do you use ? these libraries :
    IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    because you don't use conversion like integer => std_logic_vector ...

    use instead IEEE.NUMERIC_STD.ALL; if you use conversion

    you also can use generate statement for all you processes where you
    put c in d

    and what do you try to compute with you matrix, I think you're from
    the software world not hardware world
    when you write VHDL think electronic implementation not software

    if you want to synthesize this architecture : good luck
    , Mar 27, 2007
    #3
  4. VHDL_HELP

    VHDL_HELP Guest

    On 27 mar, 18:01, wrote:
    > hi
    >
    > what an horrible vhdl description !!!
    >
    > why do you use ? these libraries :
    > IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    > because you don't use conversion like integer => std_logic_vector ...
    >
    > use instead IEEE.NUMERIC_STD.ALL; if you use conversion
    >
    > you also can use generate statement for all you processes where you
    > put c in d
    >
    > and what do you try to compute with you matrix, I think you're from
    > the software world not hardware world
    > when you write VHDL think electronic implementation not software
    >
    > if you want to synthesize this architecture : good luck


    first of all sorry for my user name vhdl_help
    i m a beginner and it is my first time to use VHDL , that it is why i
    m thinking like that , i will try to do what u asked me to do , then i
    want your advices .
    thank you
    VHDL_HELP, Mar 27, 2007
    #4
  5. VHDL_HELP

    VHDL_HELP Guest

    On 27 mar, 18:01, wrote:
    > hi
    >
    > what an horrible vhdl description !!!
    >
    > why do you use ? these libraries :
    > IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    > because you don't use conversion like integer => std_logic_vector ...
    >
    > use instead IEEE.NUMERIC_STD.ALL; if you use conversion
    >
    > you also can use generate statement for all you processes where you
    > put c in d
    >
    > and what do you try to compute with you matrix, I think you're from
    > the software world not hardware world
    > when you write VHDL think electronic implementation not software
    >
    > if you want to synthesize this architecture : good luck


    i want to implement a DCT module ( module of video compressor) and i
    m really sad if i know how much i m stupid with my programs but really
    i swear that i m beginner and i want help thank you,really thank
    you , i try to get your advices
    VHDL_HELP, Mar 27, 2007
    #5
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