xc95108 problem

Discussion in 'VHDL' started by Ross Marchant, Apr 1, 2005.

  1. Hi,

    I'm using the XC95108 CPLD and Xilinx ISE 7.1i. The problem I am having is
    that outputs are inverted and only at 3 volts.

    This is my vhdl file:
    ----------------------------------------------------------------------------
    ----
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity test is
    Port ( In1 : in std_logic;
    In2 : in std_logic;
    Out1 : out std_logic;
    Out2 : out std_logic);
    end test;

    architecture Behavioral of test is

    begin
    Out1 <= In1;
    Out2 <= In2;
    Out3 <= In3;
    end Behavioral;


    This is my ucf file:
    #PACE: Start of Constraints generated by PACE

    #PACE: Start of PACE I/O Pin Assignments
    NET "In1" LOC = "P24" ;
    NET "In2" LOC = "P25" ;
    NET "Out1" LOC = "P54" ;
    NET "Out2" LOC = "P55" ;

    #PACE: Start of PACE Area Constraints

    #PACE: Start of PACE Prohibit Constraints

    #PACE: End of Constraints generated by PACE


    Now i find if i put an active low pulse on pins 24 or 25, then I will get
    the inverse of the pulse on pins 54 or 55, and only at 3 volts. What could
    be wrong!?!?! :)

    --
    Regards,
    Ross Marchant
    Ross Marchant, Apr 1, 2005
    #1
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  2. p.s.

    the Out3 <= In3; in the vhdl file isn't actually there...
    Ross Marchant, Apr 1, 2005
    #2
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