Xilinx 9.2 and Spartan-3 Starter Board

[Rutger Stoots]

Hello out there,

I don't know whether this is the right group to post this message. Still,
I'll try anyway.

For a few weeks I'm using the Xilinx ISE 9.2i WEBPack. I wrote my code in
vhdl, simulated and post-simulated it until I was satisfied with the
results. So far so good.
Then I JTAGged it to the Spartan-3 Starter Board, which went fine in Xilinx
ISE 8.1, but to my amazement doesn't work in 9.2i. It just says "failed",
the "DONE" pin doesn't go up. I looked at the properties of the bit
generator, but I don't know if nor what I'm doing wrong.
Does anyone of you know of this problem. Does anyone have a solution?

Tanks
Rutger

 

[scottcarl]

I installed ISE 9.2 service pack 1 and have had a myriad of problems. Service pack 2 just became available so I would recommend installing it immediately. If that doesn't work go back to ISE9.1 service pack 3, which has worked for just about everything I've tried, if you don't count all the hundreds of annoying Xilinx bugs.

Scott C

 

[Dave Pollum]

Hello out there,

I don't know whether this is the right group to post this message. Still,
I'll try anyway.

For a few weeks I'm using the Xilinx ISE 9.2i WEBPack. I wrote my code in
vhdl, simulated and post-simulated it until I was satisfied with the
results. So far so good.
Then I JTAGged it to the Spartan-3 Starter Board, which went fine in Xilinx
ISE 8.1, but to my amazement doesn't work in 9.2i. It just says "failed",
the "DONE" pin doesn't go up. I looked at the properties of the bit
generator, but I don't know if nor what I'm doing wrong.
Does anyone of you know of this problem. Does anyone have a solution?

Tanks
Rutger

I'm still on ISE 8.2, so I can't help you with ISE 9.2. But since
this is an ISE problem, and not a VHDL problem, you may get more
responses on comp.arch.fpga. You should also check Xilinx's web site
to see if there is a fix for this problem.
-Dave Pollum