Xilinx BRAM initialization with .coe file

[aziz]

Hello

I used core generator for generating BRAM, and use .coe file for initializing, but when I do synthesis I have warning : "the data_in (signal that is mapped to DIN (data input port of bram) is used but never assigned. This sourceless signal will be automatically connected to value 0".and ofcourse in simulation I have 0 value for that.
How Can I initialized bram with coe file ?

I used these instructions in my code "
attribute syn_black_box : boolean;
attribute syn_black_box of BSRAM0: component is true;
attribute box_type : string;
attribute box_type of BSRAM0 : component is "black_box";

Thanks