S
steve
Hi,
I've been trying to get the BRAM tied into my user logic but am seeing the
following in my Synthesis report for the user logic.
WARNING:Xst:753 -
line 677: Unconnected output port 'BRAM_Rst_B' of component 'user_logic'.
line 677: Unconnected output port 'BRAM_Clk_B' of component 'user_logic'.
line 677: Unconnected output port 'BRAM_EN_B' of component 'user_logic'.
line 677: Unconnected output port 'BRAM_WEN_B' of component 'user_logic'.
line 677: Unconnected output port 'BRAM_Addr_B' of component 'user_logic'.
line 677: Unconnected output port 'BRAM_Dout_B' of component 'user_logic'.
line 677: Unconnected input port 'BRAM_Din_B' of component 'user_logic' is
tied to default value.
but in my system assembly view , it clearly shows my logic connected into the
BRAM, at port B
System.mhs shows:
BEGIN bram_block
PARAMETER INSTANCE = Bram_Shared_Work_Area
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = CPU2BRAMIF_PORTA
BUS_INTERFACE PORTB = logic_emulator_PORTB
END
BEGIN logic_wedge
PARAMETER INSTANCE = logic_emulator
PARAMETER HW_VER = 3.01.a
PARAMETER C_BASEADDR = 0x77E00000
PARAMETER C_HIGHADDR = 0x77E01FFF
BUS_INTERFACE MSOPB = opb_v20_0
BUS_INTERFACE PORTB = logic_emulator_PORTB
END
The user logic.mpd contains:
BUS_INTERFACE BUS = PORTB, BUS_STD = XIL_BRAM, BUS_TYPE = INITIATOR
PARAMETER C_MEMSIZE = 8192, DT = integer
PARAMETER C_PORT_DWIDTH = 32, DT = integer, BUS = PORTB
PARAMETER C_PORT_AWIDTH = 32, DT = integer, BUS = PORTB
PARAMETER C_NUM_WE = 4, DT = integer, BUS = PORTB
PORT BRAM_Rst_B = BRAM_Rst, DIR = O, BUS = PORTB,
PORT BRAM_Clk_B = BRAM_Clk, DIR = O, BUS = PORTB, SIGIS =
CLK,
PORT BRAM_EN_B = BRAM_EN, DIR = O, BUS = PORTB,
PORT BRAM_WEN_B = BRAM_WEN, DIR = O, VEC = [0:C_NUM_WE-1], BUS =
PORTB,
PORT BRAM_Addr_B = BRAM_Addr, DIR = O, VEC = [0:C_PORT_AWIDTH-1], BUS =
PORTB,
PORT BRAM_Dout_B = BRAM_Dout, DIR = O, VEC = [0:C_PORT_DWIDTH-1], BUS =
PORTB,
PORT BRAM_Din_B = BRAM_Din, DIR = I, VEC = [0:C_PORT_DWIDTH-1], BUS =
PORTB,
The rest of the design compiles and works, but when i try to recover/ data
from the BRAM it is "0" even though i can see the address and other clock
signals working.
Steve
I've been trying to get the BRAM tied into my user logic but am seeing the
following in my Synthesis report for the user logic.
WARNING:Xst:753 -
line 677: Unconnected output port 'BRAM_Rst_B' of component 'user_logic'.
line 677: Unconnected output port 'BRAM_Clk_B' of component 'user_logic'.
line 677: Unconnected output port 'BRAM_EN_B' of component 'user_logic'.
line 677: Unconnected output port 'BRAM_WEN_B' of component 'user_logic'.
line 677: Unconnected output port 'BRAM_Addr_B' of component 'user_logic'.
line 677: Unconnected output port 'BRAM_Dout_B' of component 'user_logic'.
line 677: Unconnected input port 'BRAM_Din_B' of component 'user_logic' is
tied to default value.
but in my system assembly view , it clearly shows my logic connected into the
BRAM, at port B
System.mhs shows:
BEGIN bram_block
PARAMETER INSTANCE = Bram_Shared_Work_Area
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = CPU2BRAMIF_PORTA
BUS_INTERFACE PORTB = logic_emulator_PORTB
END
BEGIN logic_wedge
PARAMETER INSTANCE = logic_emulator
PARAMETER HW_VER = 3.01.a
PARAMETER C_BASEADDR = 0x77E00000
PARAMETER C_HIGHADDR = 0x77E01FFF
BUS_INTERFACE MSOPB = opb_v20_0
BUS_INTERFACE PORTB = logic_emulator_PORTB
END
The user logic.mpd contains:
BUS_INTERFACE BUS = PORTB, BUS_STD = XIL_BRAM, BUS_TYPE = INITIATOR
PARAMETER C_MEMSIZE = 8192, DT = integer
PARAMETER C_PORT_DWIDTH = 32, DT = integer, BUS = PORTB
PARAMETER C_PORT_AWIDTH = 32, DT = integer, BUS = PORTB
PARAMETER C_NUM_WE = 4, DT = integer, BUS = PORTB
PORT BRAM_Rst_B = BRAM_Rst, DIR = O, BUS = PORTB,
PORT BRAM_Clk_B = BRAM_Clk, DIR = O, BUS = PORTB, SIGIS =
CLK,
PORT BRAM_EN_B = BRAM_EN, DIR = O, BUS = PORTB,
PORT BRAM_WEN_B = BRAM_WEN, DIR = O, VEC = [0:C_NUM_WE-1], BUS =
PORTB,
PORT BRAM_Addr_B = BRAM_Addr, DIR = O, VEC = [0:C_PORT_AWIDTH-1], BUS =
PORTB,
PORT BRAM_Dout_B = BRAM_Dout, DIR = O, VEC = [0:C_PORT_DWIDTH-1], BUS =
PORTB,
PORT BRAM_Din_B = BRAM_Din, DIR = I, VEC = [0:C_PORT_DWIDTH-1], BUS =
PORTB,
The rest of the design compiles and works, but when i try to recover/ data
from the BRAM it is "0" even though i can see the address and other clock
signals working.
Steve
