Xilinx Coregen - FIFO

Discussion in 'VHDL' started by gvaglia, Jun 15, 2004.

  1. gvaglia

    gvaglia Guest

    Hi all!
    I'm using ISE 6.1 and a Spartan3 fpga. Last day I tried to instantiate a
    synchronous FIFO using Logicore.
    When I use this instance in my design the beavioural simulation works
    perfectly while the post-translate (and the others too) simulation
    don't. Looking at the RTL schematic I saw that the vector output of the
    instantiated fifo weren't connected with the output and with the other
    elements in the design. I tried to instantiate other
    memories...asynchronous fifo and so on but the problem is always the
    same. What can I do?
    The instantiated fifo working in a standalone manner (providing all
    signal throug a testbench) work fine even in the post-translate.
    Can you help me?
    Thanks a lot
    Guido

    Inviato da www.mynewsgate.net
    gvaglia, Jun 15, 2004
    #1
    1. Advertising

  2. "gvaglia" <> wrote in message news:<>...
    > Hi all!
    > I'm using ISE 6.1 and a Spartan3 fpga. Last day I tried to instantiate a
    > synchronous FIFO using Logicore.
    > When I use this instance in my design the beavioural simulation works
    > perfectly while the post-translate (and the others too) simulation
    > don't. Looking at the RTL schematic I saw that the vector output of the
    > instantiated fifo weren't connected with the output and with the other
    > elements in the design. I tried to instantiate other
    > memories...asynchronous fifo and so on but the problem is always the
    > same. What can I do?


    You could write your own code.

    All you need is a head and tail counter,
    and a dual address ram template something like:
    ------------------------------------
    constant mem_size : natural := 2**add_length;
    type mem_type is array (mem_size-1 downto 0) of
    unsigned (dat_length-1 downto 0);
    subtype ptr_type is unsigned(add_length-1 downto 0);
    --...
    begin
    ram_access : process (clk) is
    begin
    if rising_edge(clk) then
    if we = '1' then
    mem(to_integer(push_tail_ptr)) <= data_i;
    -- raw address
    end if;
    data_q <= mem(to_integer(pop_head_ptr));
    -- mem data after pop low
    end if;
    end process ram_access;
    -- ...
    -------------------------------------
    Increment the head for a push,
    the tail for a pop or both for both.

    See:
    http://groups.google.com/groups?q=lpm fifo edif.org
    for some fifo examples.

    -- Mike Treseler
    Mike Treseler, Jun 15, 2004
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Replies:
    4
    Views:
    3,000
    Weng Tianxiang
    Jun 6, 2005
  2. vu_5421
    Replies:
    0
    Views:
    462
    vu_5421
    Jan 5, 2007
  3. Norbert Stuhrmann
    Replies:
    1
    Views:
    2,214
    Norbert Stuhrmann
    Mar 25, 2007
  4. chaitu
    Replies:
    0
    Views:
    976
    chaitu
    May 31, 2007
  5. chaitu
    Replies:
    1
    Views:
    954
    Mike Treseler
    May 31, 2007
Loading...

Share This Page