P
prakash
Hi
Iam trying to synthesize using syn. pro and P&R using ISE. Iam planning
to use XIlinx-DCM and generate 66MHz (at which my design works) from
100MHz(osc. freq in board). Now in syn.pro I gave autoconstrain
frequency option. The top entity does have clk and inside the code DCM
generates clkgen0_xc2v_v_Clk0B. The mul. and div. factor I gave is 2&3.
It means my clk(100MHz) is multiplied by 2 and div. by 3 in DCM and I
will get 66.66MHz. So in the ucf file I gave for clk 100MHz. While I
translate my design in ISE, I get an warning like this.
Checking timing specifications ...
WARNING:XdmHelpers:681 - UCF definition of specification "TS_clk"
overrides the
definition found in the netlist or NCF file:
UCF: PERIOD "clk" 10000.000000 pS HIGH 50.000000 %
netlist/NCF: PERIOD:clk:4159.000000
S:HIGH:50.000000%
INFO:XdmHelpers:851 - TNM "clk", used in period specification "TS_clk",
was
traced into DCM instance "clkgen0/xc2v.v/dll0". The following new
TNM groups
and period specifications were generated at the DCM output(s):
CLKFX: TS_clkgen0_xc2v_v_Clk0B=PERIOD clkgen0_xc2v_v_Clk0B
TS_clk/0.666667
HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_clkgen0_xc2v_v_Clk0B"
references the TNM group "clkgen0_xc2v_v_Clk0B", which contains both
pads and
synchronous elements. The timing analyzer will ignore the pads for
this
specification. You might want to use a qualifier (e.g. "FFS") on the
TNM
property to remove the pads from this group.
Checking expanded design ...
Why in the generated clock I see TS_clk/0.666667 instead of TS_CLK/1.5
which makes gen. clock to be 66.666MHz.
Any help is appreciated,
Prakash
Iam trying to synthesize using syn. pro and P&R using ISE. Iam planning
to use XIlinx-DCM and generate 66MHz (at which my design works) from
100MHz(osc. freq in board). Now in syn.pro I gave autoconstrain
frequency option. The top entity does have clk and inside the code DCM
generates clkgen0_xc2v_v_Clk0B. The mul. and div. factor I gave is 2&3.
It means my clk(100MHz) is multiplied by 2 and div. by 3 in DCM and I
will get 66.66MHz. So in the ucf file I gave for clk 100MHz. While I
translate my design in ISE, I get an warning like this.
Checking timing specifications ...
WARNING:XdmHelpers:681 - UCF definition of specification "TS_clk"
overrides the
definition found in the netlist or NCF file:
UCF: PERIOD "clk" 10000.000000 pS HIGH 50.000000 %
netlist/NCF: PERIOD:clk:4159.000000
S:HIGH:50.000000%INFO:XdmHelpers:851 - TNM "clk", used in period specification "TS_clk",
was
traced into DCM instance "clkgen0/xc2v.v/dll0". The following new
TNM groups
and period specifications were generated at the DCM output(s):
CLKFX: TS_clkgen0_xc2v_v_Clk0B=PERIOD clkgen0_xc2v_v_Clk0B
TS_clk/0.666667
HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_clkgen0_xc2v_v_Clk0B"
references the TNM group "clkgen0_xc2v_v_Clk0B", which contains both
pads and
synchronous elements. The timing analyzer will ignore the pads for
this
specification. You might want to use a qualifier (e.g. "FFS") on the
TNM
property to remove the pads from this group.
Checking expanded design ...
Why in the generated clock I see TS_clk/0.666667 instead of TS_CLK/1.5
which makes gen. clock to be 66.666MHz.
Any help is appreciated,
Prakash