Xilinx FIFO CoreGen: Datacount goes to zero upon full flag

Discussion in 'VHDL' started by vu_5421, Jan 5, 2007.

  1. vu_5421

    vu_5421 Guest

    Hello all,

    In the latest FIFO Generator v3.2 (ISE 8.2i), why does the datacount go
    to zero after full flag is set? I would expect it to stay at the
    maximum depth of the FIFO even after repeated writes occur after full
    flag is set.

    Because the "datacount" goes to zero after full flag is set, you can't
    differentiate the conditions between when the FIFO is full or fifo is
    empty by just looking at the datacount itself. Xilinx helpsite tells
    you to concat the full flag with the datacount as a workaround...

    Does previous versions of the CoreGen do this as well? Or does this a
    new issue with v3.2?
     
    vu_5421, Jan 5, 2007
    #1
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