Xilinx floating-point core example please

[sam.green]

Hello,

I am looking for a VHDL example where someone has instantiated a Xilinx floating-point operator that was created with Core Generator.

I can create the core and I can get the template for my operator from the Library. I setup my entity and place the generated code. When I go to simulate, my result from the operation is all 'U's. I can post code later today.

Thanks!
Sam

 

[sam.green]

Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity float4 is
port (
a1: IN std_logic_VECTOR(31 downto 0);
b1: IN std_logic_VECTOR(31 downto 0);
operation1: IN std_logic_VECTOR(5 downto 0);
clk1: IN std_logic;
result1: OUT std_logic_VECTOR(31 downto 0));
end float4;

architecture structure of float4 is
component myFloatCore
port (
a: IN std_logic_VECTOR(31 downto 0);
b: IN std_logic_VECTOR(31 downto 0);
operation: IN std_logic_VECTOR(5 downto 0);
clk: IN std_logic;
result: OUT std_logic_VECTOR(31 downto 0));
end component;
begin
mfc : myFloatCore
port map (
a => a1,
b => b1,
operation => operation1,
clk => clk1,
result => result1);
end structure;

Note that the .xco file for myFloatCore is also visible in the project tree.

 

[vgs]

Have you changed the "maximum latency' option during the core design?
please change it to the minimum value and try simulating