xilinx logiblox and modelsim SE 5.6

Discussion in 'VHDL' started by Tim Terry, Jul 16, 2003.

  1. Tim Terry

    Tim Terry Guest

    I am having trouble using xilinx logiblox to work with modelsim SE 5.6.
    After compiling the xilinx core libs, I customised and generated a
    logiblox. I am now trying to get this device to compile in modelsim. I
    recieve 1 warning stated below:

    # Model Technology ModelSim SE vcom 5.6a Compiler 2002.04 Apr 24 2002
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Compiling entity heapram
    # -- Compiling architecture behav of heapram
    # WARNING[1]: X:/ELC/tt9/work/project/vhdl/heapCtrl/heapRam.vhd(42): No
    default binding for component: "heap". (No entity named "heap" was
    found)
    # -- Compiling configuration heapram_cfg
    # -- Loading entity heapram
    # -- Loading architecture behav of heapram
    # -- Loading package ul_utils
    # -- Loading package textio
    # -- Loading package mem_init_file_pack
    # -- Loading entity c_mem_sp_block_v1_0

    My code for the device which is simply a wrapper of a customised
    logiblox ram is below:

    --heapRam wrapper for logiblox heap device
    library IEEE;
    use IEEE.std_logic_1164.all;
    entity heapRam is
    port (
    addr: IN std_logic_VECTOR(10 downto 0);
    clk: IN std_logic;
    di: IN std_logic_VECTOR(7 downto 0);
    we: IN std_logic;
    en: IN std_logic;
    rst: IN std_logic;
    do: OUT std_logic_VECTOR(7 downto 0)
    );
    end heapRam;
    architecture behav of heapRam is
    component heap
    port (
    addr: IN std_logic_VECTOR(10 downto 0);
    clk: IN std_logic;
    di: IN std_logic_VECTOR(7 downto 0);
    we: IN std_logic;
    en: IN std_logic;
    rst: IN std_logic;
    do: OUT std_logic_VECTOR(7 downto 0)
    );
    end component;
    begin
    U0: heap
    port map (
    addr => addr,
    clk => clk,
    di => di,
    we => we,
    en => en,
    rst => rst,
    do => do
    );
    end behav;
    library xilinxcorelib;
    configuration heapRam_cfg of heapRam is
    FOR behav
    for all : heap use entity
    XilinxCoreLib.C_MEM_SP_BLOCK_V1_0(behavioral)
    generic map(
    c_has_en => 1,
    c_rst_polarity => 1,
    c_clk_polarity => 1,
    c_width => 8,
    c_has_do => 1,
    c_has_di => 1,
    c_en_polarity => 1,
    c_has_we => 1,
    c_has_rst => 1,
    c_address_width => 11,
    c_read_mif => 0,
    c_depth => 2048,
    c_pipe_stages => 0,
    c_mem_init_radix => 16,
    c_default_data => "0",
    c_mem_init_file => "X:\ELC\tt9\work\project\vhdl\work\heap.mif",
    c_we_polarity => 1,
    c_generate_mif => 1
    );
    end for;
    end for;
    end heapRam_cfg;

    Can any one tell me what I am doing wrong? if more information is needed
    please let me know.
    Thanks in advance

    Tim
     
    Tim Terry, Jul 16, 2003
    #1
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  2. Would I be correct in saying that it is not actually a Logiblox component
    and actually a product of the COREGen tool?

    I am having trouble simulating a Logiblox component because I don't have
    access to the library?


    Mike

    "Tim Terry" <> wrote in message
    news:...
    > I am having trouble using xilinx logiblox to work with modelsim SE 5.6.
    > After compiling the xilinx core libs, I customised and generated a
    > logiblox. I am now trying to get this device to compile in modelsim. I
    > recieve 1 warning stated below:
    >
    > # Model Technology ModelSim SE vcom 5.6a Compiler 2002.04 Apr 24 2002
    > # -- Loading package standard
    > # -- Loading package std_logic_1164
    > # -- Compiling entity heapram
    > # -- Compiling architecture behav of heapram
    > # WARNING[1]: X:/ELC/tt9/work/project/vhdl/heapCtrl/heapRam.vhd(42): No
    > default binding for component: "heap". (No entity named "heap" was
    > found)
    > # -- Compiling configuration heapram_cfg
    > # -- Loading entity heapram
    > # -- Loading architecture behav of heapram
    > # -- Loading package ul_utils
    > # -- Loading package textio
    > # -- Loading package mem_init_file_pack
    > # -- Loading entity c_mem_sp_block_v1_0
    >
    > My code for the device which is simply a wrapper of a customised
    > logiblox ram is below:
    >
    > --heapRam wrapper for logiblox heap device
    > library IEEE;
    > use IEEE.std_logic_1164.all;
    > entity heapRam is
    > port (
    > addr: IN std_logic_VECTOR(10 downto 0);
    > clk: IN std_logic;
    > di: IN std_logic_VECTOR(7 downto 0);
    > we: IN std_logic;
    > en: IN std_logic;
    > rst: IN std_logic;
    > do: OUT std_logic_VECTOR(7 downto 0)
    > );
    > end heapRam;
    > architecture behav of heapRam is
    > component heap
    > port (
    > addr: IN std_logic_VECTOR(10 downto 0);
    > clk: IN std_logic;
    > di: IN std_logic_VECTOR(7 downto 0);
    > we: IN std_logic;
    > en: IN std_logic;
    > rst: IN std_logic;
    > do: OUT std_logic_VECTOR(7 downto 0)
    > );
    > end component;
    > begin
    > U0: heap
    > port map (
    > addr => addr,
    > clk => clk,
    > di => di,
    > we => we,
    > en => en,
    > rst => rst,
    > do => do
    > );
    > end behav;
    > library xilinxcorelib;
    > configuration heapRam_cfg of heapRam is
    > FOR behav
    > for all : heap use entity
    > XilinxCoreLib.C_MEM_SP_BLOCK_V1_0(behavioral)
    > generic map(
    > c_has_en => 1,
    > c_rst_polarity => 1,
    > c_clk_polarity => 1,
    > c_width => 8,
    > c_has_do => 1,
    > c_has_di => 1,
    > c_en_polarity => 1,
    > c_has_we => 1,
    > c_has_rst => 1,
    > c_address_width => 11,
    > c_read_mif => 0,
    > c_depth => 2048,
    > c_pipe_stages => 0,
    > c_mem_init_radix => 16,
    > c_default_data => "0",
    > c_mem_init_file => "X:\ELC\tt9\work\project\vhdl\work\heap.mif",
    > c_we_polarity => 1,
    > c_generate_mif => 1
    > );
    > end for;
    > end for;
    > end heapRam_cfg;
    >
    > Can any one tell me what I am doing wrong? if more information is needed
    > please let me know.
    > Thanks in advance
    >
    > Tim
    >
     
    Michael Nicklas, Jul 21, 2003
    #2
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