Xilinx RAM block instanciation

[Rafal Pietrak]

Hi All!

I've just started learning VHDL and try some simple exercises. Here I have
a 'design' of a RAM-width converter: RAM that allows single byte-wide
writes, but double-byte-wide reads (byte is 5-bits here).
----------------------------------------------------------- [...library
headers omitted ....]
entity test2 is
generic ( WORD_SIZE : natural := 5;
RAM_SIZE : natural := 7);
Port ( data : inout std_logic_vector(2*WORD_SIZE-1 downto 0);
addr : in std_logic_vector(RAM_SIZE-1 downto 0); rw : in std_logic;
-- READ or WRITE csel : in std_logic); -- chip select
end test2;

architecture Behavioral of test2 is
type rft is array(2**RAM_SIZE-1 downto 0)
of std_logic_vector(WORD_SIZE-1 downto 0);
signal rf: rft;
alias pair: std_logic_vector(RAM_SIZE/2-1 downto 0)
is addr(RAM_SIZE-1 downto 1);
begin
process(csel)
begin
if rising_edge(csel) then
if rw = '1' then -- WRITE
if addr(0) = '0' then
rf(CONV_INTEGER(addr)) <= data(WORD_SIZE-1 downto 0);
else
rf(CONV_INTEGER(addr)) <= data(2*WORD_SIZE-1 downto WORD_SIZE);
end if;
end if;
end if;
end process;

data <= (others => 'Z') when (rw = '1') or (csel = '1') else
rf(CONV_INTEGER(pair & '1')) & rf(CONV_INTEGER(pair & '0'));

end Behavioral;
===============================================================

The problem is, that Xilinx ISE warns me that:
-------------------------------------------------------------
WARNING:Xst:790 - "D:/.../test2.vhd" line 41: Index value(s) does not
match array range, simulation mismatch.
INFO:Xst:1433 - Contents of array <rf> may be accessed with an index that
exceeds the array size. This could cause simulation mismatch. Entity
<test2> analyzed. Unit <test2> generated.
=============================================================

(NB: line 41: is two lined before the end of the source - "data <= ..."
assignment).

I cannot see why couple of lines above, the: "RF() <= ..." assignments are
OK, while the last assignment in architecture description rises a
WARNING??? As I cannot see any error in my source, my question is: is this
really a serious WARNING? The PAIR bus is one bit shorter then ADDR
bus, and when used in line:41 it's concatenated with the missing bit. Does
Xilinx synthesizer really misunderstands the source?

I'd appreciate any comment on what exactly this warning mean and if it
actually means nothing, how should I alter the source to avoid it.

Thex.

-R

 

[Rafal Pietrak]

Small addendum.

I've worked out, how to write this code fragment the way, that Xilinx
(IDE-7.1i) correctly synthesizes it (at least at the RTL-schematic level).

The synthesize is correct when I replace the "alias pair: ..." declaration
with the following signals:
----------------------------------------------------------
signal word_low : std_logic_vector(ADDR_BITS-1 downto 0); signal
word_high : std_logic_vector(ADDR_BITS-1 downto 0);
===========================================================

and assign data output as:
--------------------------------------------------------------
word_low <= addr(RAM_SIZE-1 downto 1) & '0';
word_high <= addr(RAM_SIZE-1 downto 1) & '1';

data <= (others => 'Z') when (rw = '1') or (csel = '1') else
rf(CONV_INTEGER(word_high)) & rf(CONV_INTEGER(word_low));
==============================================================

Can someone pls give me a hint on why is that so? Why
"CONV_INTEGER(<signal>)" gives correct synthesize while
"CONV_INTEGER(<signal-alias-less-one-bit>&'bit')" doesn't?????

I'm doing my first steps in VHDL, and this 'unpredictability' of
synthesize really bites me. I'd appreciate any comments.

-R