Xilinx RAM16X1D for a Stratix?

Discussion in 'VHDL' started by jan, Dec 7, 2003.

  1. jan

    jan Guest

    Hello,

    I am doing some porting work and require a ram
    module on a stratix fpga that behaves similarly
    to this Xilinx component. I got the following from
    http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0345_329.html

    ==>
    RAM16X1D is a 16-word by 1-bit static dual port random access memory with
    synchronous write capability. The device has two separate address ports: the
    read address (DPRA3 - DPRA0) and the write address (A3 - A0). These two
    address ports are completely asynchronous. The read address controls the
    location of the data driven out of the output pin (DPO), and the write
    address controls the destination of a valid write transaction.

    component RAM16X1D
    -- synthesis translate_off
    generic (INIT : bit_vector := X"16");
    -- synthesis translate_on
    port (DPO : out STD_ULOGIC;
    SPO : out STD_ULOGIC;
    A0 : in STD_ULOGIC;
    A1 : in STD_ULOGIC;
    A2 : in STD_ULOGIC;
    A3 : in STD_ULOGIC;
    D : in STD_ULOGIC;
    DPRA0 : in STD_ULOGIC;
    DPRA1 : in STD_ULOGIC;
    DPRA2 : in STD_ULOGIC;
    DPRA3 : in STD_ULOGIC;
    WCLK : in STD_ULOGIC;
    WE : in STD_ULOGIC);
    end component;

    thanks
    Jacques Viviers
     
    jan, Dec 7, 2003
    #1
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  2. jan wrote:
    > Hello,
    >
    > I am doing some porting work and require a ram
    > module on a stratix fpga that behaves similarly
    > to this Xilinx component. I got the following from
    > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0345_329.html


    Reread your link above and find the referenced
    code to infer this device. I expect that Quartus
    or Leo can infer an equivalent function.

    -- Mike Treseler
     
    Mike Treseler, Dec 8, 2003
    #2
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  3. jan

    Uwe Bonnes Guest

    Mike Treseler <> wrote:
    : jan wrote:
    : > Hello,
    : >
    : > I am doing some porting work and require a ram
    : > module on a stratix fpga that behaves similarly
    : > to this Xilinx component. I got the following from
    : > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0345_329.html

    : Reread your link above and find the referenced
    : code to infer this device. I expect that Quartus
    : or Leo can infer an equivalent function.

    The use of the LUT as "distributed Ram" is patented by Xilinx to my
    knowledge. Thus, similar functionality can be synthesized from FPGAs from
    other companies, but they will normal logic resources to implement the
    functionality.

    Bye
    --
    Uwe Bonnes -darmstadt.de

    Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
    --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
     
    Uwe Bonnes, Dec 8, 2003
    #3
  4. Hi Jacques,

    This is very similar to the altsyncram component of Stratix in
    single-clocked simple dual-port operation, except that the smallest
    block RAM on Stratix is 256x1. Altera does not have an equivalent of
    Xilinx' distributed RAM.

    From the link I don't know if the Xilinx RAM is pipelined. Stratix
    TriMatrix memory (Stratix' equivalent of Xilinx block ram) always have
    synchronous write, and either synchronous or pseudo-synchonous read.
    An INIT file can also be provided. If you have Quartus II, the easiest
    way to see all the options is to run Tools/MegaWizard.

    See http://www.altera.com/products/devices/stratix/features/stx-trimatrix.html

    HTH,

    -- Pete

    "jan" <> wrote in message news:<bqvg1u$l8h$>...
    > Hello,
    >
    > I am doing some porting work and require a ram
    > module on a stratix fpga that behaves similarly
    > to this Xilinx component. I got the following from
    > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0345_329.html
    >
    > ==>
    > RAM16X1D is a 16-word by 1-bit static dual port random access memory with
    > synchronous write capability. The device has two separate address ports: the
    > read address (DPRA3 - DPRA0) and the write address (A3 - A0). These two
    > address ports are completely asynchronous. The read address controls the
    > location of the data driven out of the output pin (DPO), and the write
    > address controls the destination of a valid write transaction.
    >
    > component RAM16X1D
    > -- synthesis translate_off
    > generic (INIT : bit_vector := X"16");
    > -- synthesis translate_on
    > port (DPO : out STD_ULOGIC;
    > SPO : out STD_ULOGIC;
    > A0 : in STD_ULOGIC;
    > A1 : in STD_ULOGIC;
    > A2 : in STD_ULOGIC;
    > A3 : in STD_ULOGIC;
    > D : in STD_ULOGIC;
    > DPRA0 : in STD_ULOGIC;
    > DPRA1 : in STD_ULOGIC;
    > DPRA2 : in STD_ULOGIC;
    > DPRA3 : in STD_ULOGIC;
    > WCLK : in STD_ULOGIC;
    > WE : in STD_ULOGIC);
    > end component;
    >
    > thanks
    > Jacques Viviers
     
    Peter Sommerfeld, Dec 8, 2003
    #4
  5. Peter Sommerfeld wrote:
    > Hi Jacques,
    >
    > This is very similar to the altsyncram component of Stratix in
    > single-clocked simple dual-port operation, except that the smallest
    > block RAM on Stratix is 256x1. Altera does not have an equivalent of
    > Xilinx' distributed RAM.


    Yes. Stratix has no asynchronous RAM at all,
    and 512 bits is the smallest block ram.
    Here's an example of a 512x1 that uses the whole block.

    Jacques, you can change the add_length generic to 4 for
    the closest alternate for the RAM16X1D.


    -- Mike Treseler
    --------------------


    -- $Id: dpram512x1.vhd,v 1.2 2003/12/08 21:57:59 tres Exp $
    -------------------------------------------------------------------------------
    -- M. Treseler Mon Dec 8 11:40:47 2003
    -------------------------------------------------------------------------------
    -- Infers one 512K bit memory block for Stratix
    -- Infers one large block ram for Virtex as is
    -- See comments marked --! to infer Xilinx asynchronous RAM16X1D

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;


    entity dpram512x1 is
    generic (dat_length : natural := 1;
    add_length : natural := 9 --! 4 for 16X1 RAM
    );

    port (clk : in std_ulogic;
    data : in std_logic_vector(dat_length-1 downto 0);
    rd_adr : in std_logic_vector(add_length-1 downto 0);
    wr_adr : in std_logic_vector(add_length-1 downto 0);
    we : in std_ulogic;
    q : out std_logic_vector(dat_length-1 downto 0)
    );
    end dpram512x1;

    architecture synth of dpram512x1 is
    constant mem_size : natural := 2**add_length;
    type mem_type is array (mem_size-1 downto 0) of
    std_logic_vector (dat_length-1 downto 0);
    signal mem : mem_type;
    begin

    ------------------------------------------------------------------------------
    ram_access : process (clk)
    begin
    if rising_edge(clk) then
    if we = '1' then
    mem(to_integer(unsigned(wr_adr))) <= data; -- raw address
    end if;
    end if;

    if rising_edge(clk) then --!
    q <= mem(to_integer(unsigned(rd_adr)));
    end if; --!
    -- comment 2 lines marked --! to infer Xilinx asynchronous RAM16X1D
    end process ram_access;

    end architecture synth; ------------------------------------------------------
     
    Mike Treseler, Dec 8, 2003
    #5
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