Andy,
I would rather have fixed point scaler types, maybe borrowing the ada
style, converted from "digits" to "bits" of course. The arithmetic
syntax would be much cleaner, and the results just as precise
(bit-accurate) as these vectors are, without the sizing headaches.
They'd simulate much faster than vectors too, approaching the
simulation performance of integers.
I don't doubt any of this other than the "without the sizing headaches."
When you start working with sized objects (for synthesis), you need
to somehow specify how to handle the boundaries (saturating vs modulo
based wrap around, rounding vs truncation). Consider the following:
entity e is
end e ;
architecture a of e is
-- Numeric_std
signal Y_uv, A_uv, B_uv : unsigned(7 downto 0) ;
signal Z_uv : unsigned(8 downto 0) ;
-- fixed_pkg - in Accellera vhdl-2006
signal Y_uf, A_uf, B_uf : ufixed(7 downto 0) ;
signal Z_uf : ufixed(8 downto 0) ;
-- integer based math
signal Y_int, A_int, B_int : integer range 0 to 255 ;
signal Z_int : integer range 0 to 511 ;
begin
-- Numeric_Std natively does modulo based math
Y_uv <= A_uv + B_uv ;
Z_uv <= ('0' & A_uv) + B_uv ;
-- fixed_pkg natively does full precision math
Z_uf <= A_uf + B_uf ;
Y_uf <= resize(
arg => A_uf + B_uf, -- value
size_res => Y_uf, -- size of result
overflow_style => fixed_saturate, -- alternately fixed_wrap
round_style => fixed_round -- alternately fixed_truncate
) ;
-- integer based math does full precision math:
Z_int <= A_int + B_int ;
Y_int <= (A_int + B_int) mod 255 ; -- fixed_wrap
end a ;
How do I generate a saturated value for Y_int and Y_uv?
With the current resize, synthesis tools will need to be
somewhat smart as we don't need rounding for some operations
such as addition. The example above gets more interesting
when the integers have a signed range. A long range goal
would be for the methods that are used for the integer/scalar
fixed point/real based approach be the same as for the
package based approached (assume nothing is written in
stone - meaning we can add to the packages if necessary).
If I size integers, fixed point scalars (proposed by Andy)
and real, will I still get the simulation speed-up?
What if I need an integer bigger than 32 bits?
Do I need a switch or methodology that allows me to run
fast sims which ignore the sizing (but being big enough)
and accurate sims which use the sizing?
I think you have the start of something that is a good
idea. What we need is a passionate person who can champion
a language request into the Accellera VHDL requirements
committee and then work on the enhancement in the enhancements
group - note the enhancement is not the LRM text - LRM
changes are handled by a different group.
Cheers,
Jim
--
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Jim Lewis
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SynthWorks Design Inc.
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1-503-590-4787
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