Xilinx Synthesis Problem

[venkatrav]

Hi,

I am trying to implement a certain HASH algorithm in VHDL.

The functional simulation is fine, but am facing some problems with Timing Simulation.

I tried to synthesize the code in Xilinx, and I got the following timing report

###################################################
Timing Summary:
---------------
Speed Grade: -4

Minimum period: 15.998ns (Maximum Frequency: 62.506MHz)
Minimum input arrival time before clock: 6.403ns
Maximum output required time after clock: 4.310ns
Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 15.998ns (frequency: 62.506MHz)
Total number of paths / destination ports: 13093271 / 3674
-------------------------------------------------------------------------
Delay: 15.998ns (Levels of Logic = 19)
Source: ctr_hadd1_0_1 (FF)
Destination: u_0_7 (FF)
Source Clock: clk rising
Destination Clock: clk rising

###################################################


I have adders, XOR and AND gates in my design.....but it still says it did not find a combinational path.

can this happen when synthesizing VHDL??? Please reply. If not what might be the possible reason for this??? and How can I solve it???

I am a beginner and have a little knowledge abt VHDL.

thanks,
Rav.

 

[JohnDuq]

I believe that means that you have a clocking violation, and your output signal will arrive after your input signal has latched. You need to delay your input until the next clock cycle so the output will be ready.

 

[venkatrav]

I found out that Maximum Combinational Path delay indicates the pad to pad delay iff there is a combinational path from Input to Output pins. Therefore, my design contains no such path which is a requirement......thanks...