Xilinx test bench and user group

Discussion in 'VHDL' started by Joseph A. Zammit, Feb 25, 2004.

  1. Is there any other way to specify test benches in Xilinx WebPack other
    than doing it graphicaly or using the pattern generator?

    For example i am testing a full adder through all cominbations and
    that requires quite a large testbench. Is there any other way to do
    it?

    Is there any user group/forum that is on Xilinx Coolrunner devices
    only?

    Thanks for your help

    Joseph Zammit

    Malta
     
    Joseph A. Zammit, Feb 25, 2004
    #1
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  2. Typically, special architecture is used that instantiates your design,
    generates stimuli and analyzes responses.

    architecture TB
    constant WIDTH : integer := A_WIDTH + B_WIDTH;
    signal CNT_INT: integer range 0 to 2**WIDTH - 1;
    signal CNT_VEC: std_logic_vector(WIDTH- 1 downto 0);
    alias A is CNT_VEC(A_WIDTH-1 downto 0);
    alias B is CNT_VEC(WIDTH-1 downto A_WIDTH);
    signal SUM: std_logic_vector(O_WIDTH-1 downto 0);
    begin

    CNT_VEC <= conv_std_logic_vector(CNT, WIDTH);

    UUT: entity ADDER(RTL)
    port map (A=>A, B=> B, SUM => SUM);

    process
    begin
    for I in CNT_INT'range loop
    null;
    end loop;
    wait; -- wait forever
    end;


    CLOCK : process
    begin
    CLK <= '0'; wait for PERIOD/2;
    CLK <= '1'; wait for PERIOD/2;
    end process;

    end architecture TB;
     
    valentin tihomirov, Feb 25, 2004
    #2
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  3. Joseph A. Zammit wrote:

    > Is there any other way to specify test benches in Xilinx WebPack other
    > than doing it graphicaly or using the pattern generator?


    A Testbench is nothing more than a VHDL component, than instatiates you
    design als sub-component. The testbench generates some stimuli and may
    react on the output of the sub-component.

    You are free to use the complete language, because the testbench hasn't
    to be synthesized.

    A graphical tool is nothing more than a GUI, that outputs such a plain
    text file.


    > For example i am testing a full adder through all cominbations and
    > that requires quite a large testbench.


    If you want to test your design, you should think about functional tests
    and special test in "corners" (e.g. addition with overflow). Otherwise
    the number of test vectors becomes very huge. The probability of a fault
    in a fulladder should be _very_ low. Much higher is the probability,
    that the whole adder does not work, because of a different error.

    Furthermore you should think about fault injection: Insert a
    stuck-at-zero or stuck-at-one fault at every point, you think an error
    could occur. Make a test vector, that stimulates the fault and makes the
    faul visible (not masked). Do it for all faults and you will get a much
    lower amout of nessecary test vectors.
    AFAIK some synthesis tools support test vector generation.


    Ralf
     
    Ralf Hildebrandt, Feb 25, 2004
    #3
  4. Joseph A. Zammit

    TDB Guest

    Yes, just 'add new source' and pick 'test bench'


    "Joseph A. Zammit" <> wrote in message
    news:...
    > Is there any other way to specify test benches in Xilinx WebPack other
    > than doing it graphicaly or using the pattern generator?
    >
    > For example i am testing a full adder through all cominbations and
    > that requires quite a large testbench. Is there any other way to do
    > it?
    >
    > Is there any user group/forum that is on Xilinx Coolrunner devices
    > only?
    >
    > Thanks for your help
    >
    > Joseph Zammit
    >
    > Malta
     
    TDB, Apr 21, 2004
    #4
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