Xilinx translate error : Cannot find signal "clk"

Discussion in 'VHDL' started by Rakesh Sharma, Oct 21, 2004.

  1. Hi,

    I am getting the following error in Xilinx:-

    Annotating constraints to design from file "musicmp3.ucf" ...
    ERROR:NgdBuild:755 - Line 2 in 'musicmp3.ucf': Could not find net(s) 'rxd' in
    the design. To suppress this error use the -aul switch, specify the correct
    net name or remove the constraint.
    ERROR:NgdBuild:755 - Line 4 in 'musicmp3.ucf': Could not find net(s) 'clk' in
    the design. To suppress this error use the -aul switch, specify the correct
    net name or remove the constraint.
    ERROR:parsers:11 - Encountered unrecognized constraint while parsing.
    ERROR:NgdBuild:19 - Errors found while parsing constraint file "musicmp3.ucf".

    Writing NGDBUILD log file "musicmp3.bld"...


    The UCF file looks like :-

    #PACE: Start of Constraints extracted by PACE from the Design
    NET "rxd" LOC = "P202" ;
    NET "pwm_output" LOC = "P110" ;
    NET "clk" LOC = "P80" ;


    The code goes like this :-

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_misc.all;
    use work.functions.all;


    ENTITY musicmp3 IS
    PORT (
    clk : IN std_logic;
    RxD : IN bit;
    PWM_output : OUT bit);
    END musicmp3;

    ARCHITECTURE translated OF musicmp3 IS

    COMPONENT async_receiver
    PORT (
    clk : IN std_logic;
    RxD : IN bit;
    RxD_data_ready : OUT bit;
    RxD_data : OUT bit_vector(7 DOWNTO 0);
    RxD_endofpacket : OUT bit;
    RxD_idle : OUT bit);
    END COMPONENT;


    SIGNAL RxD_data_ready : bit;
    SIGNAL RxD_data : bit_vector(7 DOWNTO 0);
    SIGNAL RxD_data_reg : bit_vector(7 DOWNTO 0);
    SIGNAL tmp : bit_vector(7 DOWNTO 0);
    SIGNAL PWM_accumulator : bit_vector(8 DOWNTO 0);
    SIGNAL PWM_output_xhdl1 : bit;


    BEGIN
    PWM_output <= PWM_output_xhdl1;
    deserialer : async_receiver
    PORT MAP (
    clk => clk,
    RxD => RxD,
    RxD_data_ready => RxD_data_ready,
    RxD_data => RxD_data);


    PROCESS
    BEGIN
    WAIT UNTIL (clk'EVENT AND clk = '1');
    IF (RxD_data_ready = '1') THEN
    RxD_data_reg <= RxD_data;
    END IF;
    END PROCESS;


    PROCESS
    VARIABLE s : BIT_VECTOR(7 downto 0);
    VARIABLE DInt : INTEGER := 0;
    VARIABLE EInt : INTEGER := 0;
    BEGIN
    WAIT UNTIL (clk'EVENT AND clk = '1');
    -- PWM_accumulator <= "0" & PWM_accumulator(7 DOWNTO 0) + RxD_data_reg;

    s := PWM_accumulator(7 DOWNTO 0);
    DInt := to_integer(s);
    EInt := to_integer(RxD_data_reg);

    DInt := DInt + EInt;

    PWM_accumulator <= to_bit(9, DInt);

    END PROCESS;
    PWM_output_xhdl1 <= PWM_accumulator(8) ;

    END translated;


    What can be wrong? Thanks in advance
    Rakesh Sharma, Oct 21, 2004
    #1
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  2. Rakesh Sharma wrote:

    > ERROR:NgdBuild:755 - Line 2 in 'musicmp3.ucf': Could not find net(s) 'rxd' in
    > the design. To suppress this error use the -aul switch, specify the correct
    > net name or remove the constraint.
    > ERROR:NgdBuild:755 - Line 4 in 'musicmp3.ucf': Could not find net(s) 'clk' in
    > the design. To suppress this error use the -aul switch, specify the correct
    > net name or remove the constraint.


    Consider declaring signals named rxd and clk.

    -- Mike Treseler
    Mike Treseler, Oct 21, 2004
    #2
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  3. Rakesh Sharma wrote:

    >Hi,
    >
    > I am getting the following error in Xilinx:-
    >
    >Annotating constraints to design from file "musicmp3.ucf" ...
    >ERROR:NgdBuild:755 - Line 2 in 'musicmp3.ucf': Could not find net(s) 'rxd' in
    > the design. To suppress this error use the -aul switch, specify the correct
    > net name or remove the constraint.
    >ERROR:NgdBuild:755 - Line 4 in 'musicmp3.ucf': Could not find net(s) 'clk' in
    > the design. To suppress this error use the -aul switch, specify the correct
    > net name or remove the constraint.
    >ERROR:parsers:11 - Encountered unrecognized constraint while parsing.
    >ERROR:NgdBuild:19 - Errors found while parsing constraint file "musicmp3.ucf".
    >
    >Writing NGDBUILD log file "musicmp3.bld"...
    >
    >
    >The UCF file looks like :-
    >
    >#PACE: Start of Constraints extracted by PACE from the Design
    >NET "rxd" LOC = "P202" ;
    >NET "pwm_output" LOC = "P110" ;
    >NET "clk" LOC = "P80" ;
    >
    >
    >The code goes like this :-
    >
    >library IEEE;
    >use IEEE.STD_LOGIC_1164.all;
    >use IEEE.std_logic_arith.all;
    >use IEEE.std_logic_misc.all;
    >use work.functions.all;
    >
    >
    >ENTITY musicmp3 IS
    > PORT (
    > clk : IN std_logic;
    > RxD : IN bit;
    > PWM_output : OUT bit);
    >END musicmp3;
    >
    >ARCHITECTURE translated OF musicmp3 IS
    >
    > COMPONENT async_receiver
    > PORT (
    > clk : IN std_logic;
    > RxD : IN bit;
    > RxD_data_ready : OUT bit;
    > RxD_data : OUT bit_vector(7 DOWNTO 0);
    > RxD_endofpacket : OUT bit;
    > RxD_idle : OUT bit);
    > END COMPONENT;
    >
    >
    > SIGNAL RxD_data_ready : bit;
    > SIGNAL RxD_data : bit_vector(7 DOWNTO 0);
    > SIGNAL RxD_data_reg : bit_vector(7 DOWNTO 0);
    > SIGNAL tmp : bit_vector(7 DOWNTO 0);
    > SIGNAL PWM_accumulator : bit_vector(8 DOWNTO 0);
    > SIGNAL PWM_output_xhdl1 : bit;
    >
    >
    >BEGIN
    > PWM_output <= PWM_output_xhdl1;
    > deserialer : async_receiver
    > PORT MAP (
    > clk => clk,
    > RxD => RxD,
    > RxD_data_ready => RxD_data_ready,
    > RxD_data => RxD_data);
    >
    >
    > PROCESS
    > BEGIN
    > WAIT UNTIL (clk'EVENT AND clk = '1');
    > IF (RxD_data_ready = '1') THEN
    > RxD_data_reg <= RxD_data;
    > END IF;
    > END PROCESS;
    >
    >
    > PROCESS
    > VARIABLE s : BIT_VECTOR(7 downto 0);
    > VARIABLE DInt : INTEGER := 0;
    > VARIABLE EInt : INTEGER := 0;
    > BEGIN
    > WAIT UNTIL (clk'EVENT AND clk = '1');
    > -- PWM_accumulator <= "0" & PWM_accumulator(7 DOWNTO 0) + RxD_data_reg;
    >
    > s := PWM_accumulator(7 DOWNTO 0);
    > DInt := to_integer(s);
    > EInt := to_integer(RxD_data_reg);
    >
    > DInt := DInt + EInt;
    >
    > PWM_accumulator <= to_bit(9, DInt);
    >
    > END PROCESS;
    > PWM_output_xhdl1 <= PWM_accumulator(8) ;
    >
    >END translated;
    >
    >
    >What can be wrong? Thanks in advance
    >
    >

    Assign a signal to the output and the optimizer won't remove your logic.
    You must have an error saying your FPGA is empty.

    Regards
    Thomas
    Thomas Rudloff, Oct 22, 2004
    #3
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