XST: How to select the architecture for synthesis?

Discussion in 'VHDL' started by Mathias Schmalisch, Feb 23, 2005.

  1. Hi,

    I have an VHDL toplevel entity with multiple architectures. If I try
    to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool,
    then only the last architecture will be synthesized.

    Therefore my question: Is it possible to select the architecture that
    will be synthesized and how this work?

    Best Regards
    Mathias
     
    Mathias Schmalisch, Feb 23, 2005
    #1
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  2. On 2005-02-23, Mathias Schmalisch <> wrote:
    > I have an VHDL toplevel entity with multiple architectures. If I try
    > to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool,
    > then only the last architecture will be synthesized.
    >
    > Therefore my question: Is it possible to select the architecture that
    > will be synthesized and how this work?


    In principle you can do that in VHDL using the
    configuration specification like

    for all : xxx use entity yyy(rtl)

    ...but my experience is that very few of synthesis programs support it.
    At least Synopsys Design Compiler doesn't. I don't know a better
    solution except that just to comment out other architectures and leave
    just one. If anyone knows a better way, let me know.
     
    Tuukka Toivonen, Feb 23, 2005
    #2
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  3. Re: How to select the architecture for synthesis?

    Hi,

    any particular reason why you do have several architectures within your
    entity?

    Usually as you have already mentioned the last architecture gets
    synthesized.
    You might check the XST manuals or the Xilinx homepage if pragmas might
    help.

    According to the constraints guide for ise6.3i p. 821 xst can handle
    translate_on and translate_off.
    The constraints guide is downloadable as zipped pdf from the XILINX homepage

    HTH

    Ansgar

    --
    Attention please, reply address is invalid, please remove "_xxx_" ro reply
    "Mathias Schmalisch" <> schrieb im Newsbeitrag
    news:...
    > Hi,
    >
    > I have an VHDL toplevel entity with multiple architectures. If I try
    > to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool,
    > then only the last architecture will be synthesized.
    >
    > Therefore my question: Is it possible to select the architecture that
    > will be synthesized and how this work?
    >
    > Best Regards
    > Mathias
     
    Ansgar Bambynek, Feb 23, 2005
    #3
  4. In comp.arch.fpga Tuukka Toivonen <> wrote:
    > I don't know a better solution except that just to comment out other architectures
    > and leave just one. If anyone knows a better way, let me know.


    A "pre-compiler" before the synthesis tool is no option? Some
    very nice conditional synthesis is also possible with text tools
    like:

    gnu-make, awk/sed or m4. Just as a hint...

    WD
    --
     
    Walter Dvorak, Feb 23, 2005
    #4
  5. Mathias Schmalisch

    Hal Murray Guest

    > A "pre-compiler" before the synthesis tool is no option? Some
    >very nice conditional synthesis is also possible with text tools
    >like:
    >
    > gnu-make, awk/sed or m4. Just as a hint...


    The standard c pre processor that handles #if, #ifdef and #define
    works on any input file.

    try man cpp

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    The suespammers.org mail server is located in California. So are all my
    other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
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    These are my opinions, not necessarily my employer's. I hate spam.
     
    Hal Murray, Feb 26, 2005
    #5
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